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-rw-r--r--hw/i2c/allwinner-i2c.c2
-rw-r--r--hw/i2c/aspeed_i2c.c17
-rw-r--r--hw/i2c/bcm2835_i2c.c2
-rw-r--r--hw/i2c/bitbang_i2c.c2
-rw-r--r--hw/i2c/core.c2
-rw-r--r--hw/i2c/exynos4210_i2c.c2
-rw-r--r--hw/i2c/i2c_mux_pca954x.c6
-rw-r--r--hw/i2c/imx_i2c.c13
-rw-r--r--hw/i2c/microbit_i2c.c2
-rw-r--r--hw/i2c/mpc_i2c.c2
-rw-r--r--hw/i2c/npcm7xx_smbus.c2
-rw-r--r--hw/i2c/omap_i2c.c180
-rw-r--r--hw/i2c/pm_smbus.c1
-rw-r--r--hw/i2c/pmbus_device.c2
-rw-r--r--hw/i2c/ppc4xx_i2c.c2
-rw-r--r--hw/i2c/smbus_eeprom.c2
-rw-r--r--hw/i2c/smbus_ich9.c4
-rw-r--r--hw/i2c/smbus_slave.c2
18 files changed, 122 insertions, 123 deletions
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
index 66d6431..fe887e1 100644
--- a/hw/i2c/allwinner-i2c.c
+++ b/hw/i2c/allwinner-i2c.c
@@ -438,7 +438,7 @@ static void allwinner_i2c_realize(DeviceState *dev, Error **errp)
s->bus = i2c_init_bus(dev, "i2c");
}
-static void allwinner_i2c_class_init(ObjectClass *klass, void *data)
+static void allwinner_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index a8fbb9f..83fb906 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1263,7 +1263,7 @@ static const Property aspeed_i2c_properties[] = {
TYPE_MEMORY_REGION, MemoryRegion *),
};
-static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
+static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1390,7 +1390,8 @@ static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data)
aspeed_i2c_bus_raise_interrupt(bus);
}
-static void aspeed_i2c_bus_slave_class_init(ObjectClass *klass, void *data)
+static void aspeed_i2c_bus_slave_class_init(ObjectClass *klass,
+ const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
@@ -1451,7 +1452,7 @@ static const Property aspeed_i2c_bus_properties[] = {
AspeedI2CState *),
};
-static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data)
+static void aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1483,7 +1484,7 @@ static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus)
return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)];
}
-static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data)
+static void aspeed_2400_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
@@ -1517,7 +1518,7 @@ static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus)
return bus->pool;
}
-static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data)
+static void aspeed_2500_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
@@ -1547,7 +1548,7 @@ static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus)
return bus->irq;
}
-static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data)
+static void aspeed_2600_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
@@ -1571,7 +1572,7 @@ static const TypeInfo aspeed_2600_i2c_info = {
.class_init = aspeed_2600_i2c_class_init,
};
-static void aspeed_1030_i2c_class_init(ObjectClass *klass, void *data)
+static void aspeed_1030_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
@@ -1595,7 +1596,7 @@ static const TypeInfo aspeed_1030_i2c_info = {
.class_init = aspeed_1030_i2c_class_init,
};
-static void aspeed_2700_i2c_class_init(ObjectClass *klass, void *data)
+static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
diff --git a/hw/i2c/bcm2835_i2c.c b/hw/i2c/bcm2835_i2c.c
index 67bfdef..be11cca 100644
--- a/hw/i2c/bcm2835_i2c.c
+++ b/hw/i2c/bcm2835_i2c.c
@@ -258,7 +258,7 @@ static const VMStateDescription vmstate_bcm2835_i2c = {
}
};
-static void bcm2835_i2c_class_init(ObjectClass *klass, void *data)
+static void bcm2835_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
index de5f5aa..e020f31 100644
--- a/hw/i2c/bitbang_i2c.c
+++ b/hw/i2c/bitbang_i2c.c
@@ -222,7 +222,7 @@ static void gpio_i2c_init(Object *obj)
qdev_init_gpio_out(dev, &s->out, 1);
}
-static void gpio_i2c_class_init(ObjectClass *klass, void *data)
+static void gpio_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index 26bb185..4b6345b 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -401,7 +401,7 @@ static bool i2c_slave_match(I2CSlave *candidate, uint8_t address,
return false;
}
-static void i2c_slave_class_init(ObjectClass *klass, void *data)
+static void i2c_slave_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);
I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
diff --git a/hw/i2c/exynos4210_i2c.c b/hw/i2c/exynos4210_i2c.c
index b1d0009..9d0c1cd 100644
--- a/hw/i2c/exynos4210_i2c.c
+++ b/hw/i2c/exynos4210_i2c.c
@@ -309,7 +309,7 @@ static void exynos4210_i2c_init(Object *obj)
s->bus = i2c_init_bus(dev, "i2c");
}
-static void exynos4210_i2c_class_init(ObjectClass *klass, void *data)
+static void exynos4210_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c
index 779cc4e..a8ef640 100644
--- a/hw/i2c/i2c_mux_pca954x.c
+++ b/hw/i2c/i2c_mux_pca954x.c
@@ -172,13 +172,13 @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel)
return pca954x->bus[channel];
}
-static void pca9546_class_init(ObjectClass *klass, void *data)
+static void pca9546_class_init(ObjectClass *klass, const void *data)
{
Pca954xClass *s = PCA954X_CLASS(klass);
s->nchans = PCA9546_CHANNEL_COUNT;
}
-static void pca9548_class_init(ObjectClass *klass, void *data)
+static void pca9548_class_init(ObjectClass *klass, const void *data)
{
Pca954xClass *s = PCA954X_CLASS(klass);
s->nchans = PCA9548_CHANNEL_COUNT;
@@ -215,7 +215,7 @@ static const Property pca954x_props[] = {
DEFINE_PROP_STRING("name", Pca954xState, name),
};
-static void pca954x_class_init(ObjectClass *klass, void *data)
+static void pca954x_class_init(ObjectClass *klass, const void *data)
{
I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index d62213b..d26177c 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -79,13 +79,12 @@ static void imx_i2c_reset(DeviceState *dev)
static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
{
- /*
- * raise an interrupt if the device is enabled and it is configured
- * to generate some interrupts.
- */
- if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
+ if (imx_i2c_is_enabled(s)) {
s->i2sr |= I2SR_IIF;
- qemu_irq_raise(s->irq);
+
+ if (imx_i2c_interrupt_is_enabled(s)) {
+ qemu_irq_raise(s->irq);
+ }
}
}
@@ -297,7 +296,7 @@ static void imx_i2c_realize(DeviceState *dev, Error **errp)
s->bus = i2c_init_bus(dev, NULL);
}
-static void imx_i2c_class_init(ObjectClass *klass, void *data)
+static void imx_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
index 06fbd18..2291d63 100644
--- a/hw/i2c/microbit_i2c.c
+++ b/hw/i2c/microbit_i2c.c
@@ -105,7 +105,7 @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
}
-static void microbit_i2c_class_init(ObjectClass *klass, void *data)
+static void microbit_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c
index 913d044..25f91b7 100644
--- a/hw/i2c/mpc_i2c.c
+++ b/hw/i2c/mpc_i2c.c
@@ -334,7 +334,7 @@ static void mpc_i2c_realize(DeviceState *dev, Error **errp)
i2c->bus = i2c_init_bus(dev, "i2c");
}
-static void mpc_i2c_class_init(ObjectClass *klass, void *data)
+static void mpc_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c
index 22d68fc..179852a 100644
--- a/hw/i2c/npcm7xx_smbus.c
+++ b/hw/i2c/npcm7xx_smbus.c
@@ -1075,7 +1075,7 @@ static const VMStateDescription vmstate_npcm7xx_smbus = {
},
};
-static void npcm7xx_smbus_class_init(ObjectClass *klass, void *data)
+static void npcm7xx_smbus_class_init(ObjectClass *klass, const void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
index a641db2..751bf74 100644
--- a/hw/i2c/omap_i2c.c
+++ b/hw/i2c/omap_i2c.c
@@ -55,16 +55,16 @@ struct OMAPI2CState {
uint16_t test;
};
-#define OMAP2_INTR_REV 0x34
-#define OMAP2_GC_REV 0x34
+#define OMAP2_INTR_REV 0x34
+#define OMAP2_GC_REV 0x34
static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
qemu_set_irq(s->irq, s->stat & s->mask);
- if ((s->dma >> 15) & 1) /* RDMA_EN */
- qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
- if ((s->dma >> 7) & 1) /* XDMA_EN */
- qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
+ if ((s->dma >> 15) & 1) /* RDMA_EN */
+ qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
+ if ((s->dma >> 7) & 1) /* XDMA_EN */
+ qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
}
static void omap_i2c_fifo_run(OMAPI2CState *s)
@@ -74,25 +74,25 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
if (!i2c_bus_busy(s->bus))
return;
- if ((s->control >> 2) & 1) { /* RM */
- if ((s->control >> 1) & 1) { /* STP */
+ if ((s->control >> 2) & 1) { /* RM */
+ if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
- s->control &= ~(1 << 1); /* STP */
+ s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
s->txlen = 0;
- } else if ((s->control >> 9) & 1) { /* TRX */
+ } else if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->txlen)
ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) &
0xff) >= 0);
- s->stat |= 1 << 4; /* XRDY */
+ s->stat |= 1 << 4; /* XRDY */
} else {
while (s->rxlen < 4)
s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
- s->stat |= 1 << 3; /* RRDY */
+ s->stat |= 1 << 3; /* RRDY */
}
} else {
- if ((s->control >> 9) & 1) { /* TRX */
+ if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->count_cur && s->txlen) {
ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) &
@@ -100,12 +100,12 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --;
}
if (ack && s->count_cur)
- s->stat |= 1 << 4; /* XRDY */
+ s->stat |= 1 << 4; /* XRDY */
else
- s->stat &= ~(1 << 4); /* XRDY */
+ s->stat &= ~(1 << 4); /* XRDY */
if (!s->count_cur) {
- s->stat |= 1 << 2; /* ARDY */
- s->control &= ~(1 << 10); /* MST */
+ s->stat |= 1 << 2; /* ARDY */
+ s->control &= ~(1 << 10); /* MST */
}
} else {
while (s->count_cur && s->rxlen < 4) {
@@ -113,26 +113,26 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --;
}
if (s->rxlen)
- s->stat |= 1 << 3; /* RRDY */
+ s->stat |= 1 << 3; /* RRDY */
else
- s->stat &= ~(1 << 3); /* RRDY */
+ s->stat &= ~(1 << 3); /* RRDY */
}
if (!s->count_cur) {
- if ((s->control >> 1) & 1) { /* STP */
+ if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
- s->control &= ~(1 << 1); /* STP */
+ s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
s->txlen = 0;
} else {
- s->stat |= 1 << 2; /* ARDY */
- s->control &= ~(1 << 10); /* MST */
+ s->stat |= 1 << 2; /* ARDY */
+ s->control &= ~(1 << 10); /* MST */
}
}
}
- s->stat |= (!ack) << 1; /* NACK */
+ s->stat |= (!ack) << 1; /* NACK */
if (!ack)
- s->control &= ~(1 << 1); /* STP */
+ s->control &= ~(1 << 1); /* STP */
}
static void omap_i2c_reset(DeviceState *dev)
@@ -163,16 +163,16 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
uint16_t ret;
switch (offset) {
- case 0x00: /* I2C_REV */
- return s->revision; /* REV */
+ case 0x00: /* I2C_REV */
+ return s->revision; /* REV */
- case 0x04: /* I2C_IE */
+ case 0x04: /* I2C_IE */
return s->mask;
- case 0x08: /* I2C_STAT */
+ case 0x08: /* I2C_STAT */
return s->stat | (i2c_bus_busy(s->bus) << 12);
- case 0x0c: /* I2C_IV */
+ case 0x0c: /* I2C_IV */
if (s->revision >= OMAP2_INTR_REV)
break;
ret = ctz32(s->stat & s->mask);
@@ -185,18 +185,18 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
omap_i2c_interrupts_update(s);
return ret;
- case 0x10: /* I2C_SYSS */
- return (s->control >> 15) & 1; /* I2C_EN */
+ case 0x10: /* I2C_SYSS */
+ return (s->control >> 15) & 1; /* I2C_EN */
- case 0x14: /* I2C_BUF */
+ case 0x14: /* I2C_BUF */
return s->dma;
- case 0x18: /* I2C_CNT */
- return s->count_cur; /* DCOUNT */
+ case 0x18: /* I2C_CNT */
+ return s->count_cur; /* DCOUNT */
- case 0x1c: /* I2C_DATA */
+ case 0x1c: /* I2C_DATA */
ret = 0;
- if (s->control & (1 << 14)) { /* BE */
+ if (s->control & (1 << 14)) { /* BE */
ret |= ((s->fifo >> 0) & 0xff) << 8;
ret |= ((s->fifo >> 8) & 0xff) << 0;
} else {
@@ -204,7 +204,7 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
ret |= ((s->fifo >> 0) & 0xff) << 0;
}
if (s->rxlen == 1) {
- s->stat |= 1 << 15; /* SBD */
+ s->stat |= 1 << 15; /* SBD */
s->rxlen = 0;
} else if (s->rxlen > 1) {
if (s->rxlen > 2)
@@ -214,41 +214,41 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
/* XXX: remote access (qualifier) error - what's that? */
}
if (!s->rxlen) {
- s->stat &= ~(1 << 3); /* RRDY */
- if (((s->control >> 10) & 1) && /* MST */
- ((~s->control >> 9) & 1)) { /* TRX */
- s->stat |= 1 << 2; /* ARDY */
- s->control &= ~(1 << 10); /* MST */
+ s->stat &= ~(1 << 3); /* RRDY */
+ if (((s->control >> 10) & 1) && /* MST */
+ ((~s->control >> 9) & 1)) { /* TRX */
+ s->stat |= 1 << 2; /* ARDY */
+ s->control &= ~(1 << 10); /* MST */
}
}
- s->stat &= ~(1 << 11); /* ROVR */
+ s->stat &= ~(1 << 11); /* ROVR */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
return ret;
- case 0x20: /* I2C_SYSC */
+ case 0x20: /* I2C_SYSC */
return 0;
- case 0x24: /* I2C_CON */
+ case 0x24: /* I2C_CON */
return s->control;
- case 0x28: /* I2C_OA */
+ case 0x28: /* I2C_OA */
return s->addr[0];
- case 0x2c: /* I2C_SA */
+ case 0x2c: /* I2C_SA */
return s->addr[1];
- case 0x30: /* I2C_PSC */
+ case 0x30: /* I2C_PSC */
return s->divider;
- case 0x34: /* I2C_SCLL */
+ case 0x34: /* I2C_SCLL */
return s->times[0];
- case 0x38: /* I2C_SCLH */
+ case 0x38: /* I2C_SCLH */
return s->times[1];
- case 0x3c: /* I2C_SYSTEST */
- if (s->test & (1 << 15)) { /* ST_EN */
+ case 0x3c: /* I2C_SYSTEST */
+ if (s->test & (1 << 15)) { /* ST_EN */
s->test ^= 0xa;
return s->test;
} else
@@ -267,17 +267,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
int nack;
switch (offset) {
- case 0x00: /* I2C_REV */
- case 0x0c: /* I2C_IV */
- case 0x10: /* I2C_SYSS */
+ case 0x00: /* I2C_REV */
+ case 0x0c: /* I2C_IV */
+ case 0x10: /* I2C_SYSS */
OMAP_RO_REG(addr);
return;
- case 0x04: /* I2C_IE */
+ case 0x04: /* I2C_IE */
s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
break;
- case 0x08: /* I2C_STAT */
+ case 0x08: /* I2C_STAT */
if (s->revision < OMAP2_INTR_REV) {
OMAP_RO_REG(addr);
return;
@@ -288,40 +288,40 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
omap_i2c_interrupts_update(s);
break;
- case 0x14: /* I2C_BUF */
+ case 0x14: /* I2C_BUF */
s->dma = value & 0x8080;
- if (value & (1 << 15)) /* RDMA_EN */
- s->mask &= ~(1 << 3); /* RRDY_IE */
- if (value & (1 << 7)) /* XDMA_EN */
- s->mask &= ~(1 << 4); /* XRDY_IE */
+ if (value & (1 << 15)) /* RDMA_EN */
+ s->mask &= ~(1 << 3); /* RRDY_IE */
+ if (value & (1 << 7)) /* XDMA_EN */
+ s->mask &= ~(1 << 4); /* XRDY_IE */
break;
- case 0x18: /* I2C_CNT */
- s->count = value; /* DCOUNT */
+ case 0x18: /* I2C_CNT */
+ s->count = value; /* DCOUNT */
break;
- case 0x1c: /* I2C_DATA */
+ case 0x1c: /* I2C_DATA */
if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */
break;
}
s->fifo <<= 16;
s->txlen += 2;
- if (s->control & (1 << 14)) { /* BE */
+ if (s->control & (1 << 14)) { /* BE */
s->fifo |= ((value >> 8) & 0xff) << 8;
s->fifo |= ((value >> 0) & 0xff) << 0;
} else {
s->fifo |= ((value >> 0) & 0xff) << 8;
s->fifo |= ((value >> 8) & 0xff) << 0;
}
- s->stat &= ~(1 << 10); /* XUDF */
+ s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2)
- s->stat &= ~(1 << 4); /* XRDY */
+ s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
break;
- case 0x20: /* I2C_SYSC */
+ case 0x20: /* I2C_SYSC */
if (s->revision < OMAP2_INTR_REV) {
OMAP_BAD_REG(addr);
return;
@@ -332,9 +332,9 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
}
break;
- case 0x24: /* I2C_CON */
+ case 0x24: /* I2C_CON */
s->control = value & 0xcf87;
- if (~value & (1 << 15)) { /* I2C_EN */
+ if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV) {
omap_i2c_reset(DEVICE(s));
}
@@ -351,14 +351,14 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
__func__);
break;
}
- if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
- nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
- (~value >> 9) & 1); /* TRX */
- s->stat |= nack << 1; /* NACK */
- s->control &= ~(1 << 0); /* STT */
+ if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
+ nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
+ (~value >> 9) & 1); /* TRX */
+ s->stat |= nack << 1; /* NACK */
+ s->control &= ~(1 << 0); /* STT */
s->fifo = 0;
if (nack)
- s->control &= ~(1 << 1); /* STP */
+ s->control &= ~(1 << 1); /* STP */
else {
s->count_cur = s->count;
omap_i2c_fifo_run(s);
@@ -367,34 +367,34 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
}
break;
- case 0x28: /* I2C_OA */
+ case 0x28: /* I2C_OA */
s->addr[0] = value & 0x3ff;
break;
- case 0x2c: /* I2C_SA */
+ case 0x2c: /* I2C_SA */
s->addr[1] = value & 0x3ff;
break;
- case 0x30: /* I2C_PSC */
+ case 0x30: /* I2C_PSC */
s->divider = value;
break;
- case 0x34: /* I2C_SCLL */
+ case 0x34: /* I2C_SCLL */
s->times[0] = value;
break;
- case 0x38: /* I2C_SCLH */
+ case 0x38: /* I2C_SCLH */
s->times[1] = value;
break;
- case 0x3c: /* I2C_SYSTEST */
+ case 0x3c: /* I2C_SYSTEST */
s->test = value & 0xf80f;
- if (value & (1 << 11)) /* SBB */
+ if (value & (1 << 11)) /* SBB */
if (s->revision >= OMAP2_INTR_REV) {
s->stat |= 0x3f;
omap_i2c_interrupts_update(s);
}
- if (value & (1 << 15)) { /* ST_EN */
+ if (value & (1 << 15)) { /* ST_EN */
qemu_log_mask(LOG_UNIMP,
"%s: System Test not supported\n", __func__);
}
@@ -413,7 +413,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
- case 0x1c: /* I2C_DATA */
+ case 0x1c: /* I2C_DATA */
if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */
break;
@@ -421,9 +421,9 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
s->fifo <<= 8;
s->txlen += 1;
s->fifo |= value & 0xff;
- s->stat &= ~(1 << 10); /* XUDF */
+ s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2)
- s->stat &= ~(1 << 4); /* XRDY */
+ s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
break;
@@ -515,7 +515,7 @@ static const Property omap_i2c_properties[] = {
DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
};
-static void omap_i2c_class_init(ObjectClass *klass, void *data)
+static void omap_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
index 3eed811..4e685fd 100644
--- a/hw/i2c/pm_smbus.c
+++ b/hw/i2c/pm_smbus.c
@@ -205,7 +205,6 @@ out:
error:
s->smb_stat |= STS_DEV_ERR;
- return;
}
static void smb_transaction_start(PMSMBus *s)
diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c
index ba1d2fd..853dc4b 100644
--- a/hw/i2c/pmbus_device.c
+++ b/hw/i2c/pmbus_device.c
@@ -1902,7 +1902,7 @@ static void pmbus_device_finalize(Object *obj)
g_free(pmdev->pages);
}
-static void pmbus_device_class_init(ObjectClass *klass, void *data)
+static void pmbus_device_class_init(ObjectClass *klass, const void *data)
{
SMBusDeviceClass *k = SMBUS_DEVICE_CLASS(klass);
diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c
index 7b124a7..09d4c49 100644
--- a/hw/i2c/ppc4xx_i2c.c
+++ b/hw/i2c/ppc4xx_i2c.c
@@ -354,7 +354,7 @@ static void ppc4xx_i2c_init(Object *o)
bitbang_i2c_init(&s->bitbang, s->bus);
}
-static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
+static void ppc4xx_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index e3e96d4..0a1088f 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -137,7 +137,7 @@ static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
}
}
-static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data)
+static void smbus_eeprom_class_initfn(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass);
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index 208f263..956c9b5 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -118,7 +118,7 @@ static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope)
qbus_build_aml(bus, scope);
}
-static void ich9_smb_class_init(ObjectClass *klass, void *data)
+static void ich9_smb_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -145,7 +145,7 @@ static const TypeInfo ich9_smb_info = {
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(ICH9SMBState),
.class_init = ich9_smb_class_init,
- .interfaces = (InterfaceInfo[]) {
+ .interfaces = (const InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ TYPE_ACPI_DEV_AML_IF },
{ },
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 9f9afc2..cfb61c8 100644
--- a/hw/i2c/smbus_slave.c
+++ b/hw/i2c/smbus_slave.c
@@ -201,7 +201,7 @@ static int smbus_i2c_send(I2CSlave *s, uint8_t data)
return 0;
}
-static void smbus_device_class_init(ObjectClass *klass, void *data)
+static void smbus_device_class_init(ObjectClass *klass, const void *data)
{
I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
generated by cgit v1.1 at 2025-07-01 23:06:34 +0000