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authorStefan Hajnoczi <stefanha@redhat.com>2025-05-19 14:00:54 -0400
committerStefan Hajnoczi <stefanha@redhat.com>2025-05-19 14:00:54 -0400
commit2af4a82ab2cce3412ffc92cd4c96bd870e33bc8e (patch)
treedde0b929a0de9426e58e73f7def191f4deca1770 /tests/functional/test_mipsel_tuxrun.py
parent757a34115e7491744a63dfc3d291fd1de5297ee2 (diff)
parente7cb99bfd1afc5cf2265a122bcfeab36eff7489a (diff)
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Merge tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu into stagingHEADstagingmaster
First RISC-V PR for 10.1 * Add support for RIMT to virt machine ACPI * Don't allow PMP RLB to bypass rule privileges * Fix checks on writes to pmpcfg in Smepmp MML mode * Generate strided vector loads/stores with tcg nodes * Improve Microchip Polarfire SoC customization * Use tcg ops generation to emulate whole reg rvv loads/stores * Expand the probe_pages helper function to handle probe flags * Fix type conflict of GLib function pointers * Fix endless translation loop on big endian systems * Use tail pseudoinstruction for calling tail * Fix some RISC-V vector instruction corner cases * MAINTAINERS: Add common-user/host/riscv to RISC-V section * Fix write_misa vs aligned next_pc * KVM CSR fixes * Virt machine memmap usage cleanup # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmgqreUACgkQr3yVEwxT # gBMurA//WAX4X+aNi6keCr20Ffv3gUnkPPeVewLLKOrZZ7h5oyWtRcSQvwDBSr8C # vzs4Rf492iNljnbRj09KYkLB8Qq/QH2Ixl+IgG8ueJAHJ8WdG6HYrrDxcONwgL1K # lQrRaDrMCFjU35uDlejfuvWWEmb4GKDMfj/wxs5wgNvnHgNhThmVaWQysx8KHYU+ # tevPQj5s4mvVGztGRSHIZQ8bth7oVUQR5CsKngGEmVLS2L6yVYTUN5ZhB5g6Ikrq # jKn44cROLfvv+0zPB9Lgu7eKauA/h8SckjCV+dGoMDB5J5M/TvwS118VHOjNVEQZ # yLx6/BdLp3SRPwbvu9jn6vjms95iZSJXXdnY+Cg4MqAbuIRQK66n6Zoa3LjbEk2U # zsf03uYUla9CBs6VQJmF7yjks3AbWokpZ9WSsGIcHJgXe8pEUeEsWOgiBhifJ5bD # Hljlkiw1gHCjhtc2aWEH0aBwM7896lmdct70JmkjQ4uZKkFSqJ8y5l0Gm3lvgvdO # OEPyMbZ6hSO4UZovcpeFtOoXteCUVthvqz0mADoQAtG+2qoX0k+9h8v305fhlti+ # bXJfu1QPsQqCYMrv4ZSTbRg0uC8m7CHnA+coC0XnCcMwEk9ZBl373/cnQYWsmqo8 # lxZmXLvpaN9CEzjOmZhXUsOvIqAJdM1sYPWnoXJ71t7mn4QEOPA= # =dFjk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 May 2025 00:04:53 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu: (56 commits) hw/riscv/virt.c: remove 'long' casts in fmt strings hw/riscv/virt.c: use s->memmap in finalize_fdt() functions hw/riscv/virt.c: use s->memmap in create_fdt_virtio() hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path hw/riscv/virt.c: use s->memmap in create_fdt() path hw/riscv/virt.c: add 'base' arg in create_fw_cfg() hw/riscv/virt.c: use s->memmap in virt_machine_done() hw/riscv/virt.c: remove trivial virt_memmap references hw/riscv/virt.c: enforce s->memmap use in machine_init() target/riscv/kvm: add scounteren CSR target/riscv/kvm: read/write KVM regs via env size target/riscv/kvm: add senvcfg CSR target/riscv/kvm: do not read unavailable CSRs target/riscv/kvm: add kvm_csr_cfgs[] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro target/riscv/kvm: turn u32/u64 reg functions into macros target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg() target/riscv/kvm: minor fixes/tweaks target/riscv: Fix write_misa vs aligned next_pc target/riscv: Move insn_len to internals.h ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'tests/functional/test_mipsel_tuxrun.py')
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