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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-12-21 16:50:26 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-12-24 08:32:15 -0800 |
| commit | e4a8e093dc74be049f4829831dce76e5edab0003 (patch) | |
| tree | 20354b9913086ac3a535e06e4d28057f88710d14 /target/mips | |
| parent | 59abfb444e1d9654e15f85c50d09a3366e4c1c1e (diff) | |
| download | qemu-e4a8e093dc74be049f4829831dce76e5edab0003.zip qemu-e4a8e093dc74be049f4829831dce76e5edab0003.tar.gz qemu-e4a8e093dc74be049f4829831dce76e5edab0003.tar.bz2 | |
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
Convert all targets simultaneously, as the gen_intermediate_code
function disappears from the target. While there are possible
workarounds, they're larger than simply performing the conversion.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/cpu.c | 1 | ||||
| -rw-r--r-- | target/mips/tcg/tcg-internal.h | 2 | ||||
| -rw-r--r-- | target/mips/tcg/translate.c | 4 |
3 files changed, 5 insertions, 2 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1b0cf6d..e3af02a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -547,6 +547,7 @@ static const Property mips_cpu_properties[] = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, + .translate_code = mips_translate_code, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index aef032c..74fc130 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -16,6 +16,8 @@ #include "cpu.h" void mips_tcg_init(void); +void mips_translate_code(CPUState *cs, TranslationBlock *tb, + int *max_insns, vaddr pc, void *host_pc); void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index bd1ef4e..78b848a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15231,8 +15231,8 @@ static const TranslatorOps mips_tr_ops = { .tb_stop = mips_tr_tb_stop, }; -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - vaddr pc, void *host_pc) +void mips_translate_code(CPUState *cs, TranslationBlock *tb, + int *max_insns, vaddr pc, void *host_pc) { DisasContext ctx; |