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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-01-24 11:02:49 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-01-27 09:38:15 +0100 |
| commit | a22acbb252fe308416aafae8069beaf039578f14 (patch) | |
| tree | 77fab4bb1db893a3e6d8bd1fb9ae0b6fdc92daad /scripts/xml-preprocess.py | |
| parent | 668f29e1713b879fa32af213cc2820ea589034d0 (diff) | |
| download | qemu-a22acbb252fe308416aafae8069beaf039578f14.zip qemu-a22acbb252fe308416aafae8069beaf039578f14.tar.gz qemu-a22acbb252fe308416aafae8069beaf039578f14.tar.bz2 | |
aspeed/wdt: Support software reset mode for AST2600
On the AST2400 and AST2500 platforms, the system can only be reset by enabling
the WDT (Watchdog Timer) and waiting for the WDT timeout. However, starting
from the AST2600 platform, the reset event can be triggered directly and
intentionally by software, without relying on the WDT timeout.
This mechanism, referred to as "software restart", is implemented in hardware.
When using the software restart mechanism, the WDT counter is not enabled.
To trigger a reset generation in software mode, write 0xAEEDF123 to register
0x24 and software mode reset only support SOC reset mode.
A new function, "aspeed_wdt_is_soc_reset_mode", is introduced to determine
whether the SoC reset mode is active.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250124030249.1706996-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'scripts/xml-preprocess.py')
0 files changed, 0 insertions, 0 deletions