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| author | Atish Patra <atishp@rivosinc.com> | 2025-01-10 00:21:33 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | f2548886b3dff228b82e91808553616c4b8d14a8 (patch) | |
| tree | 836cbe1b2f51de491ab06d17fb2b9f175d215f00 /scripts/xml-preprocess-test.py | |
| parent | 5e33a20827150345350bede07e26a1bae320e682 (diff) | |
| download | qemu-f2548886b3dff228b82e91808553616c4b8d14a8.zip qemu-f2548886b3dff228b82e91808553616c4b8d14a8.tar.gz qemu-f2548886b3dff228b82e91808553616c4b8d14a8.tar.bz2 | |
target/riscv: Add properties for counter delegation ISA extensions
This adds the properties for counter delegation ISA extensions
(Smcdeleg/Ssccfg). Definitions of new registers and and implementation
will come in the next set of patches.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-5-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/xml-preprocess-test.py')
0 files changed, 0 insertions, 0 deletions