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| author | Atish Patra <atishp@rivosinc.com> | 2025-01-10 00:21:38 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | 2a754d6957e70889e7208f4d2d6bdb9714508c9b (patch) | |
| tree | 23286cc6983b91e96c039991cd37622ea0f4987b /scripts/xml-preprocess-test.py | |
| parent | 04ff272d588695a2a4c328347e767b24fa241408 (diff) | |
| download | qemu-2a754d6957e70889e7208f4d2d6bdb9714508c9b.zip qemu-2a754d6957e70889e7208f4d2d6bdb9714508c9b.tar.gz qemu-2a754d6957e70889e7208f4d2d6bdb9714508c9b.tar.bz2 | |
target/riscv: Add implied rule for counter delegation extensions
The counter delegation/configuration extensions depend on the following
extensions.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
Add an implied rule so that these extensions are enabled by default
if the sscfg extension is enabled.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-10-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/xml-preprocess-test.py')
0 files changed, 0 insertions, 0 deletions