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| author | Clément Léger <cleger@rivosinc.com> | 2025-01-10 13:54:33 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | 0aadf8162a77a03c79e35e76e16b99cd18ef7916 (patch) | |
| tree | 229b19a106b44ed0b0b2fc5102417adc9a7c00f6 /scripts/xml-preprocess-test.py | |
| parent | 507957eb2acfd321646c98bc853d6c8bafe628d2 (diff) | |
| download | qemu-0aadf8162a77a03c79e35e76e16b99cd18ef7916.zip qemu-0aadf8162a77a03c79e35e76e16b99cd18ef7916.tar.gz qemu-0aadf8162a77a03c79e35e76e16b99cd18ef7916.tar.bz2 | |
target/riscv: Add Ssdbltrp CSRs handling
Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
{H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
presence of the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-3-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/xml-preprocess-test.py')
0 files changed, 0 insertions, 0 deletions