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author | Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> | 2025-07-22 17:37:36 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2025-08-01 16:48:50 +0100 |
commit | 97b3d732afec9b165c33697452e31267a845338f (patch) | |
tree | a6330d055f7060fcec343b7991d1c3da083270e8 /scripts/tracetool/backend/syslog.py | |
parent | 35cca0f95ff5345f54c11d116efc8940a0dab8aa (diff) | |
download | qemu-97b3d732afec9b165c33697452e31267a845338f.zip qemu-97b3d732afec9b165c33697452e31267a845338f.tar.gz qemu-97b3d732afec9b165c33697452e31267a845338f.tar.bz2 |
target/arm: Fix handling of setting SVE registers from gdb
The code to handle setting SVE registers via the gdbstub is broken:
* it sets each pair of elements in the zregs[].d[] array in the
wrong order for the most common (little endian) case: the least
significant 64-bit value comes first
* it makes no attempt to handle target_endian()
* it does a simple copy out of the (target endian) gdbstub buffer
into the (host endan) zregs data structure, which is wrong on
big endian hosts
Fix all these problems:
* use ldq_p() to read from the gdbstub buffer
* check target_big_endian() to see if we need to handle the
128-bit values the opposite way around
Cc: qemu-stable@nongnu.org
Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
Message-id: 20250722173736.2332529-3-vacha.bhavsar@oss.qualcomm.com
[PMM: adjusted commit message, fixed spacing]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/tracetool/backend/syslog.py')
0 files changed, 0 insertions, 0 deletions