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authorDeepak Gupta <debug@rivosinc.com>2025-03-05 22:46:35 -0800
committerAlistair Francis <alistair.francis@wdc.com>2025-03-19 16:33:01 +1000
commit86c78b280607fcff787866a03374047c65037a90 (patch)
treedd7c6a7c6b4431780c059b3e31fbc6422ba3ef02 /scripts/tracetool/backend/syslog.py
parent17288e38bebf20121c4aa20b264e661a7fa50ed8 (diff)
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target/riscv: fix access permission checks for CSR_SSP
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But rather rules clearly specified in section "22.2.1. Shadow Stack Pointer (ssp) CSR access contr" in the priv spec. Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls for zicfiss". Thanks to Adam Zabrocki for bringing this to attention. Reported-by: Adam Zabrocki <azabrocki@nvidia.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250306064636.452396-1-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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