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author | Steven Lee <steven_lee@aspeedtech.com> | 2025-05-02 18:34:41 +0800 |
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committer | Cédric Le Goater <clg@redhat.com> | 2025-05-05 09:38:55 +0200 |
commit | 541da2604fe157d9db5995808097230a9f966b4a (patch) | |
tree | 7a994c143feecaa85d2f5b0ace689f15e2433450 /scripts/rust/rustc_args.py | |
parent | c528f10dce8eeaabe97f216d6488a6b8509b7067 (diff) | |
download | qemu-541da2604fe157d9db5995808097230a9f966b4a.zip qemu-541da2604fe157d9db5995808097230a9f966b4a.tar.gz qemu-541da2604fe157d9db5995808097230a9f966b4a.tar.bz2 |
hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A1 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.
Difference from AST2700:
- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I924bf1a657f1e83f9e16d6673713f4a06ecdb496
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-6-steven_lee@aspeedtech.com
[ clg: removed local 'Error* err' in aspeed_soc_ast27x0ssp_realize() ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'scripts/rust/rustc_args.py')
0 files changed, 0 insertions, 0 deletions