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author | Peter Maydell <peter.maydell@linaro.org> | 2025-03-07 10:08:20 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2025-03-07 10:08:20 +0000 |
commit | 4aecd4b442d7abb4355896d878ffc9b028625b01 (patch) | |
tree | 9754ce97ecbe541cac4f2b906c3913819192285f /scripts/rust/rustc_args.py | |
parent | bdd641541fbef0a27bf9f60e7eba6f8a31d4706c (diff) | |
download | qemu-4aecd4b442d7abb4355896d878ffc9b028625b01.zip qemu-4aecd4b442d7abb4355896d878ffc9b028625b01.tar.gz qemu-4aecd4b442d7abb4355896d878ffc9b028625b01.tar.bz2 |
target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
EL1 virt timer. This is almost correct, but the underlying
CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02
always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
we're at EL2 and HCR_EL2.E2H is 1.
We were getting this wrong, because we ended up in
gt_virt_cnt_offset() and did the E2H check.
Factor out the tval read/write calculation from the selection of the
offset, so that we can special case gt_virt_tval_read() and
gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org
Diffstat (limited to 'scripts/rust/rustc_args.py')
0 files changed, 0 insertions, 0 deletions