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| author | Ivan Klokov <ivan.klokov@syntacore.com> | 2025-01-09 12:10:43 +0300 |
|---|---|---|
| committer | Fabiano Rosas <farosas@suse.de> | 2025-01-17 11:48:43 -0300 |
| commit | 1addf57177a5646f86ede4eee385932b0214ab72 (patch) | |
| tree | 34c585653f196f2db82539cdd433036754f54b61 /scripts/render_block_graph.py | |
| parent | 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5 (diff) | |
| download | qemu-1addf57177a5646f86ede4eee385932b0214ab72.zip qemu-1addf57177a5646f86ede4eee385932b0214ab72.tar.gz qemu-1addf57177a5646f86ede4eee385932b0214ab72.tar.bz2 | |
target/riscv: Add RISC-V CSR qtest support
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Acked-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Diffstat (limited to 'scripts/render_block_graph.py')
0 files changed, 0 insertions, 0 deletions