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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-10-06 16:46:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-10-06 16:46:48 +0100 |
| commit | 3f0cddeee1f266d43c956581f3050058360a810d (patch) | |
| tree | 296d08b674ac4debe7505b9b5547ce1eb6894174 /scripts/qemu.py | |
| parent | 3919e60b6efd9a86a0e6ba637aa584222855ac3a (diff) | |
| download | qemu-3f0cddeee1f266d43c956581f3050058360a810d.zip qemu-3f0cddeee1f266d43c956581f3050058360a810d.tar.gz qemu-3f0cddeee1f266d43c956581f3050058360a810d.tar.bz2 | |
target/arm: Restore SPSEL to correct CONTROL register on exception return
On exception return for v8M, the SPSEL bit in the EXC_RETURN magic
value should be restored to the SPSEL bit in the CONTROL register
banked specified by the EXC_RETURN.ES bit.
Add write_v7m_control_spsel_for_secstate() which behaves like
write_v7m_control_spsel() but allows the caller to specify which
CONTROL bank to use, reimplement write_v7m_control_spsel() in
terms of it, and use it in exception return.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1506092407-26985-6-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'scripts/qemu.py')
0 files changed, 0 insertions, 0 deletions