diff options
| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2025-06-04 14:43:27 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:48 +1000 |
| commit | f31ba686a9387640a905ac70fe682c15c461a134 (patch) | |
| tree | 18ae4442edbe2553b045e2248221575e8f8e3a33 /scripts/qapi/source.py | |
| parent | 455c0fa9eef7f27e5b50ebd2b6fe3447c4f1ca51 (diff) | |
| download | qemu-f31ba686a9387640a905ac70fe682c15c461a134.zip qemu-f31ba686a9387640a905ac70fe682c15c461a134.tar.gz qemu-f31ba686a9387640a905ac70fe682c15c461a134.tar.bz2 | |
target/riscv/cpu.c: add 'sdtrig' in riscv,isa
We have support for sdtrig for awhile but we are not advertising it. It
is enabled by default via the 'debug' flag. Use the same flag to also
advertise sdtrig.
Add an exception in disable_priv_spec_isa_exts() to avoid spamming
warnings for 'sdtrig' for vendor CPUs like sifive_u.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250604174329.1147549-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi/source.py')
0 files changed, 0 insertions, 0 deletions