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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-06-18 16:00:05 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-03 13:41:57 +0200 |
| commit | a6ca5dfccc2b584d2f7bf31fb488fc178e967972 (patch) | |
| tree | c58f1a4b5a9cbfc51de7068d1a3be0d2e4c04889 /scripts/qapi/source.py | |
| parent | 51ac481bff88723ef4c101925082fab03bba200a (diff) | |
| download | qemu-a6ca5dfccc2b584d2f7bf31fb488fc178e967972.zip qemu-a6ca5dfccc2b584d2f7bf31fb488fc178e967972.tar.gz qemu-a6ca5dfccc2b584d2f7bf31fb488fc178e967972.tar.bz2 | |
hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700
According to the datasheet:
BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter.
BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished.
Firmware polls BIT[6] to determine when measurement is complete.
The flag can be cleared by writing BIT[1] to 0.
To simulate this hardware behavior in QEMU:
If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid
firmware hanging during polling.
If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match
hardware semantics.
The initial value of this register is initialized to 0x80, reflecting the
default value confirmed from an EVB register dump.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'scripts/qapi/source.py')
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