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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-29 21:23:17 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-02-02 17:00:55 +0000 |
| commit | 93722b6f6a6ef0ab0544f20440a2f6b951103dcb (patch) | |
| tree | 96edd9a76b5cb0b434029ed9c1479a6ea6ca2338 /scripts/qapi/source.py | |
| parent | 9c431a43a62255402a6bbe9a01b0464e73b30fe4 (diff) | |
| download | qemu-93722b6f6a6ef0ab0544f20440a2f6b951103dcb.zip qemu-93722b6f6a6ef0ab0544f20440a2f6b951103dcb.tar.gz qemu-93722b6f6a6ef0ab0544f20440a2f6b951103dcb.tar.bz2 | |
hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
When the block is disabled, all registers are reset with the
exception of the ECSPI_CONREG. It is initialized to zero
when the instance is created.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
chapter 21.7.3: Control Register (ECSPIx_CONREG)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com
[bmeng: add a 'common_reset' function that does most of reset operation]
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi/source.py')
0 files changed, 0 insertions, 0 deletions