diff options
author | Frank Chang <frank.chang@sifive.com> | 2024-06-25 19:46:24 +0800 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-26 23:06:00 +1000 |
commit | f04f7709203c539bec29258288ba846b993db8e3 (patch) | |
tree | c7eb6d01ba0b43f430655564a23e1d39086ce00f /scripts/qapi/parser.py | |
parent | c165408779ae3a5aceddc8603471b1c20e58fcae (diff) | |
download | qemu-f04f7709203c539bec29258288ba846b993db8e3.zip qemu-f04f7709203c539bec29258288ba846b993db8e3.tar.gz qemu-f04f7709203c539bec29258288ba846b993db8e3.tar.bz2 |
target/riscv: Introduce extension implied rules definition
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offset of the extension defined in RISCVCPUConfig. 'ext' will also
serve as the key of the hash tables to look up the rule in the following
commit.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240625114629.27793-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi/parser.py')
0 files changed, 0 insertions, 0 deletions