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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-12-18 09:53:30 -0300 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:47 +1000 |
commit | e7acc1cb934bfada058c726f39548407cfb2a772 (patch) | |
tree | 2aa9e0b1333db16fc869917efa3021a0901a85c6 /scripts/qapi/parser.py | |
parent | ab77a9d5074f87b7ff3df605b26d87c1909d0c01 (diff) | |
download | qemu-e7acc1cb934bfada058c726f39548407cfb2a772.zip qemu-e7acc1cb934bfada058c726f39548407cfb2a772.tar.gz qemu-e7acc1cb934bfada058c726f39548407cfb2a772.tar.bz2 |
target/riscv/cpu.c: add riscv_cpu_is_32bit()
Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit.
The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check
the first CPU of a given hart array, not any given CPU.
Create a helper to retrieve the info for any given CPU, not the first
CPU of the hart array. The helper is using the same 32 bit check that
riscv_cpu_satp_mode_finalize() was doing.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-23-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi/parser.py')
0 files changed, 0 insertions, 0 deletions