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| author | Yanfeng Liu <yfliu2008@qq.com> | 2024-12-16 05:36:35 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:34 +1000 |
| commit | e9952b3631b97f35d06052e0f3ec7ce812c9b539 (patch) | |
| tree | 84cf37069ddc45cd8602303ccec7ae78d271594b /scripts/qapi-gen.py | |
| parent | d4ce7ef4b3b867e4d369f6024cf5f217f7bc2202 (diff) | |
| download | qemu-e9952b3631b97f35d06052e0f3ec7ce812c9b539.zip qemu-e9952b3631b97f35d06052e0f3ec7ce812c9b539.tar.gz qemu-e9952b3631b97f35d06052e0f3ec7ce812c9b539.tar.bz2 | |
riscv/gdbstub: add V bit to priv reg
This adds virtualization mode (V bit) as bit(2) of register `priv`
per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1.
Note that GDB may display `INVALID` tag for `priv` reg when V bit
is set, this doesn't affect actual access to the bit though.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_1993B55C24DE7979BF34B200F78287002907@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi-gen.py')
0 files changed, 0 insertions, 0 deletions