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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-01-13 14:44:55 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-01-27 09:38:15 +0100 |
| commit | 9cdca151f32eb9840aa5a1b3ba01a5b533d27686 (patch) | |
| tree | b2ac96b3723e94161e75940f6978f6a6627a16f6 /scripts/python_qmp_updater.py | |
| parent | 8bc691bed881b37079405984334a59e0b6abba01 (diff) | |
| download | qemu-9cdca151f32eb9840aa5a1b3ba01a5b533d27686.zip qemu-9cdca151f32eb9840aa5a1b3ba01a5b533d27686.tar.gz qemu-9cdca151f32eb9840aa5a1b3ba01a5b533d27686.tar.bz2 | |
aspeed/soc: Support Timer for AST2700
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_0000
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3 = 0x12C1_00C0
Base Address of Timer 4 = 0x12C1_0100
Base Address of Timer 5 = 0x12C1_0140
Base Address of Timer 6 = 0x12C1_0180
Base Address of Timer 7 = 0x12C1_01C0
The interrupt of TIMER0 to TIMER7 as following.
GICINT16 = TIMER 0 interrupt
GICINT17 = TIMER 1 interrupt
GICINT18 = TIMER 2 interrupt
GICINT19 = TIMER 3 interrupt
GICINT20 = TIMER 4 interrupt
GICINT21 = TIMER 5 interrupt
GICINT22 = TIMER 6 interrupt
GICINT23 = TIMER 7 interrupt
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20250113064455.1660564-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'scripts/python_qmp_updater.py')
0 files changed, 0 insertions, 0 deletions