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authorVacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>2025-09-09 16:10:11 +0000
committerPeter Maydell <peter.maydell@linaro.org>2025-09-16 17:31:54 +0100
commit030f0ba11767c7bd4148d9cd4f63e299d38139b3 (patch)
tree90e58bcc265dda5fca25f6cb9cbc88d84c9eb1f5 /scripts/lib/kdoc/kdoc_parser.py
parent71cda981208ebcfa403d8e3451d1d5bdef0b0931 (diff)
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target/arm: Added support for SME register exposure to GDB
The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality for AArch64 targets, this patch registers the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Note that according to the GDB documentation the ZA register is defined as a vector of bytes; however the target description xml retrieved when using gdb natively on a host with SME capabilities represents the ZA register as a vector of vectors of bytes, so this is a GDB documentation error. We follow GDB's own gdbstub implementation and represent the ZA register as a vector of vectors of bytes as is done by GDB here: https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b176199d1381d7/gdb/features/aarch64-sme.c#L50 Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> Message-id: 20250909161012.2561593-3-vacha.bhavsar@oss.qualcomm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed minor checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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