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authorJamin Lin <jamin_lin@aspeedtech.com>2025-01-13 14:44:53 +0800
committerCédric Le Goater <clg@redhat.com>2025-01-27 09:38:15 +0100
commitef2385bb3797a594c85c14452d89a2d884d1df44 (patch)
treee836406e9178e43a8a8cf00265617b5edd0e7e57 /rust/qemu-api-macros
parentbf8a471a38774800d77f58949bcaea4ca26390a7 (diff)
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hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations
The register set have a significant change in AST2700. The TMC00-TMC3C are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional, TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1, respectively. Besides, each TIMER has their own control and interrupt status register. In other words, users are able to set control and interrupt status for TIMER0 in one register. Both aspeed_timer_read and aspeed_timer_write callback functions are not compatible AST2700. Introduce common read and write functions for ASPEED timers. Modify the aspeed_timer_read and aspeed_timer_write functions to delegate to SoC-specific callbacks first. Update the AST2400, AST2500, AST2600 and AST1030 specific read and write functions to call the common implementations for common register accesses. This refactoring improves the organization of call delegation and prepares the codebase for future SoC-specific specializations, such as the AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250113064455.1660564-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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