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| author | Max Chou <max.chou@sifive.com> | 2025-01-24 18:14:47 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-04 15:42:54 +1000 |
| commit | ffd455963f230c7dc04965609d6675da687a5a78 (patch) | |
| tree | 5a412c89332598ac98b5d68f331806744e7cff09 /rust/qemu-api-macros/src | |
| parent | b55538ea22c6474e62a311f5993f0f84caeb4131 (diff) | |
| download | qemu-ffd455963f230c7dc04965609d6675da687a5a78.zip qemu-ffd455963f230c7dc04965609d6675da687a5a78.tar.gz qemu-ffd455963f230c7dc04965609d6675da687a5a78.tar.bz2 | |
target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0
According to the Vector Reduction Operations section in the RISC-V "V"
Vector Extension spec,
"If vl=0, no operation is performed and the destination register is not
updated."
The vd should be updated when vl is larger than 0.
Fixes: fe5c9ab1fc ("target/riscv: vector single-width integer reduction instructions")
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250124101452.2519171-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api-macros/src')
0 files changed, 0 insertions, 0 deletions