aboutsummaryrefslogtreecommitdiff
path: root/rust/hw
diff options
context:
space:
mode:
authorRakesh Jeyasingh <rakeshjb010@gmail.com>2025-04-07 23:43:26 +0530
committerPaolo Bonzini <pbonzini@redhat.com>2025-04-23 10:35:23 +0200
commitefc5603292bfde97fd82fabcedce86310bedbc65 (patch)
tree48af2c63266d80a2fa3c4dd9327c51c1933514d1 /rust/hw
parentd031d2fac9b94126ed0cd440da9e69e229d88aef (diff)
downloadqemu-efc5603292bfde97fd82fabcedce86310bedbc65.zip
qemu-efc5603292bfde97fd82fabcedce86310bedbc65.tar.gz
qemu-efc5603292bfde97fd82fabcedce86310bedbc65.tar.bz2
rust/hw/char/pl011: Extract extract DR read logic into separate function
- Split `read()` DR case into `read_data_register()` Signed-off-by: Rakesh Jeyasingh <rakeshjb010@gmail.com> Link: https://lore.kernel.org/r/20250407181327.171563-2-rakeshjb010@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'rust/hw')
-rw-r--r--rust/hw/char/pl011/src/device.rs39
1 files changed, 20 insertions, 19 deletions
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index bf88e0b..87153cd 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -190,25 +190,7 @@ impl PL011Registers {
let mut update = false;
let result = match offset {
- DR => {
- self.flags.set_receive_fifo_full(false);
- let c = self.read_fifo[self.read_pos];
- if self.read_count > 0 {
- self.read_count -= 1;
- self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
- }
- if self.read_count == 0 {
- self.flags.set_receive_fifo_empty(true);
- }
- if self.read_count + 1 == self.read_trigger {
- self.int_level &= !Interrupt::RX.0;
- }
- // Update error bits.
- self.receive_status_error_clear.set_from_data(c);
- // Must call qemu_chr_fe_accept_input
- update = true;
- u32::from(c)
- }
+ DR => self.read_data_register(&mut update),
RSR => u32::from(self.receive_status_error_clear),
FR => u32::from(self.flags),
FBRD => self.fbrd,
@@ -306,6 +288,25 @@ impl PL011Registers {
false
}
+ fn read_data_register(&mut self, update: &mut bool) -> u32 {
+ self.flags.set_receive_fifo_full(false);
+ let c = self.read_fifo[self.read_pos];
+
+ if self.read_count > 0 {
+ self.read_count -= 1;
+ self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
+ }
+ if self.read_count == 0 {
+ self.flags.set_receive_fifo_empty(true);
+ }
+ if self.read_count + 1 == self.read_trigger {
+ self.int_level &= !Interrupt::RX.0;
+ }
+ self.receive_status_error_clear.set_from_data(c);
+ *update = true;
+ u32::from(c)
+ }
+
#[inline]
#[must_use]
fn loopback_tx(&mut self, value: registers::Data) -> bool {