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authorFabiano Rosas <farosas@suse.de>2024-09-11 11:16:51 -0300
committerRichard Henderson <richard.henderson@linaro.org>2024-09-22 06:55:21 +0200
commit8bded2e73e80823a67f730140788a3c5e60bf4b5 (patch)
tree4ee3cf0083cf3eda8da03cbdf3cfe0905409d0fc /python/scripts
parent50695fb83e22ad011708b738d24c6c67d6296aaa (diff)
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target/ppc: Fix lxvx/stxvx facility check
The XT check for the lxvx/stxvx instructions is currently inverted. This was introduced during the move to decodetree. >From the ISA: Chapter 7. Vector-Scalar Extension Facility Load VSX Vector Indexed X-form lxvx XT,RA,RB if TX=0 & MSR.VSX=0 then VSX_Unavailable() if TX=1 & MSR.VEC=0 then Vector_Unavailable() ... Let XT be the value 32×TX + T. The code currently does the opposite: if (paired || a->rt >= 32) { REQUIRE_VSX(ctx); } else { REQUIRE_VECTOR(ctx); } This was already fixed for lxv/stxv at commit "2cc0e449d1 (target/ppc: Fix lxv/stxv MSR facility check)", but the indexed forms were missed. Cc: qemu-stable@nongnu.org Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from legacy to decodtree") Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Claudio Fontana <cfontana@suse.de> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20240911141651.6914-1-farosas@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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