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| author | Alireza Sanaee <alireza.sanaee@huawei.com> | 2024-09-13 15:31:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-09-13 15:31:47 +0100 |
| commit | 676624d757abe0adcfa648ed3d4d44697997382f (patch) | |
| tree | 4ce4888bcdac1e1dfea97e2a4f98bc5a8cc86ced /python/scripts/vendor.py | |
| parent | d54ffa54fbe0691f8e953b867cbe65642efbdf67 (diff) | |
| download | qemu-676624d757abe0adcfa648ed3d4d44697997382f.zip qemu-676624d757abe0adcfa648ed3d4d44697997382f.tar.gz qemu-676624d757abe0adcfa648ed3d4d44697997382f.tar.bz2 | |
target/arm/tcg: refine cache descriptions with a wrapper
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One function `make_ccsidr` supports
two cases by carrying a parameter as FORMAT that can be LEGACY and
CCIDX which determines the specification of the register.
For CCSIDR register, 32 bit version follows specification [1].
Conversely, 64 bit version follows specification [2].
[1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R
edition, https://developer.arm.com/documentation/ddi0406
[2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture,
https://developer.arm.com/documentation/ddi0487/latest/
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240903144550.280-1-alireza.sanaee@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/scripts/vendor.py')
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