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author | Stefan Hajnoczi <stefanha@redhat.com> | 2025-07-21 12:21:49 -0400 |
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committer | Stefan Hajnoczi <stefanha@redhat.com> | 2025-07-21 12:21:50 -0400 |
commit | bb153e7960b24fb31b36b4230e4d1d008ae2f129 (patch) | |
tree | bf7850cefd61713b888b61e485ff0461a7984d92 /linux-user/plugin-api.c | |
parent | b4f0b382fe241a1c57ab42ec538f49db45193df7 (diff) | |
parent | 7724ca9a772594b96939ff549c74f46e11d7870b (diff) | |
download | qemu-bb153e7960b24fb31b36b4230e4d1d008ae2f129.zip qemu-bb153e7960b24fb31b36b4230e4d1d008ae2f129.tar.gz qemu-bb153e7960b24fb31b36b4230e4d1d008ae2f129.tar.bz2 |
Merge tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* hvf: arm: Remove $pc from trace_hvf_data_abort()
* target/arm: Correct encoding of Debug Communications Channel registers
* hw/misc/ivshmem-pci: Improve error handling
* target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode
* host-utils: Drop workaround for buggy Apple Clang __builtin_subcll()
* hw/misc/max78000_aes: Comment Internal Key Storage
* docs: Fix Aspeed title
* Implement a handful of missing FEAT_SVE_B16_B16 insns
* Fix bugs in FMAXQV, FMINQV, etc
* Fix assert in LD1Q decode
* hvf: arm: Add permission check in GIC sysreg handlers
* hvf: arm: Emulate ICC_RPR_EL1 accesses properly
* accel/hvf: Display executable bit as 'X'
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmh+OlgZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3klRD/0QvWyi0z0wbBdIKGi8kury
# VP/S1FcqP2w9l0jUAmINxsOYu/+ql8w3t6m2jxlTOYZc9rNauQrxRYGD1GdqfJVn
# VCYN47OHRye+iMH6c5jdKyJTi3n2uvT2g8anh2Yt18xOey45Pwr2fTs8rje3N5sH
# fvv1mNaeGyA7wgXEY9Z4tEvW19ZPsuKIBd4Ea7klDXwUpTmmQkJMVTKyz7/TefqK
# YicpM9E4dMxwNvW/8zrsVH505E4s15OytIjhDci30v2M7Uh3tUIRKo+s44Kk7cEq
# HIwO/ra1HEhp8xGU2UfRf643EF1k7A0VUgetHSxYbi1gIknjiSU8Ohnd268CgY7G
# /UbjgjFu5mcJgBvoNCwGy0iuCkEfRZ+veq24OjL6GbMvt2utCm9Rumu5KLemLpvW
# mB4RexjbT+FDldhz8Ub42sR96UpZ0TSEfwjOswHibA4Zk4o2S6fRv0OqaBMB2dKU
# MhcMdBdPXe3SmecRlYoqde+RCUyIOMD46uiJYrBhG6Nfn6SgcnS+ZGB960veaH2r
# p5lvyJIBn3/a1KwOET9z5Gp3C6l4TXgJjIaCB4qAWHxeBR/AIobRC71heCc0uPU+
# J3Nm5/p6rcz0vjzs1To0VuXM57qNpQJWu0Un+8CDjpXJ0piyBk4o2iu1dw26bsMs
# yrgqlMfDsXNlK/yUdykAbw==
# =rQ+N
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 21 Jul 2025 09:02:16 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu:
accel/hvf: Display executable bit as 'X'
hvf: arm: Emulate ICC_RPR_EL1 accesses properly
hvf: arm: Add permission check in GIC sysreg handlers
target/arm: Make LD1Q decode and trans fn agree about a->u
target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV
target/arm: Don't nest H() macro calls in SVE DO_REDUCE
target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
target/arm: Add BFMLA, BFMLS (indexed)
target/arm: Add BFMLA, BFMLS (vectors)
target/arm: Add BFMUL (indexed)
target/arm: Add BFMIN, BFMAX (predicated)
target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)
docs: Fix Aspeed title
hw/misc/max78000_aes: Comment Internal Key Storage
host-utils: Drop workaround for buggy Apple Clang __builtin_subcll()
target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode
hw/misc/ivshmem-pci: Improve error handling
target/arm: Correct encoding of Debug Communications Channel registers
hvf: arm: Remove $pc from trace_hvf_data_abort()
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'linux-user/plugin-api.c')
0 files changed, 0 insertions, 0 deletions