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author | Jay Chang <jay.chang@sifive.com> | 2025-07-01 11:00:21 +0800 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-30 10:59:26 +1000 |
commit | 86bc3a0abf10072081cddd8dff25aa72c60e67b8 (patch) | |
tree | c2be25100602f36312b07b98b0bc3785b8f06478 /linux-user/arm/target_flat.h | |
parent | e443ba03361b63218e6c3aa4f73d2cb5b9b1d372 (diff) | |
download | qemu-86bc3a0abf10072081cddd8dff25aa72c60e67b8.zip qemu-86bc3a0abf10072081cddd8dff25aa72c60e67b8.tar.gz qemu-86bc3a0abf10072081cddd8dff25aa72c60e67b8.tar.bz2 |
target/riscv: Restrict midelegh access to S-mode harts
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentially the same as Smaia except
excluding the machine-level CSRs and behavior not directly visible to
supervisor level."
Since midelegh is an AIA machine-mode CSR, add Smaia extension check in
aia_smode32 predicate.
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Message-ID: <20250701030021.99218-3-jay.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'linux-user/arm/target_flat.h')
0 files changed, 0 insertions, 0 deletions