Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into stagingHEADstagingmaster

Third RISC-V PR for 10.1

* Fix pmp range wraparound on zero
* Update FADT and MADT versions in ACPI tables
* Fix target register read when source is inactive
* Add riscv_hwprobe entry to linux-user strace list
* Do not call GETPC() in check_ret_from_m_mode()
* Revert "Generate strided vector loads/stores with tcg nodes."
* Fix exception type when VU accesses supervisor CSRs
* Restrict mideleg/medeleg/medelegh access to S-mode harts
* Restrict midelegh access to S-mode harts

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* tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu:
  target/riscv: Restrict midelegh access to S-mode harts
  target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
  target/riscv: Fix exception type when VU accesses supervisor CSRs
  riscv: Revert "Generate strided vector loads/stores with tcg nodes."
  target/riscv: do not call GETPC() in check_ret_from_m_mode()
  linux-user/strace.list: add riscv_hwprobe entry
  intc/riscv_aplic: Fix target register read when source is inactive
  tests/data/acpi/riscv64: Update expected FADT and MADT
  hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
  bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
  target/riscv: Fix pmp range wraparound on zero

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

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