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author | Zhao Liu <zhao1.liu@intel.com> | 2024-11-01 16:33:23 +0800 |
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committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-05 23:32:25 +0000 |
commit | 34230ce5a97b898a53032b958841e74fde0bdac1 (patch) | |
tree | 58a43f8839b1b0d733f1a4e0583d2bb61036aa8d /include/hw/boards.h | |
parent | 6e64c8ef8c15e459ef2423bc0214537bbca6c50f (diff) | |
download | qemu-34230ce5a97b898a53032b958841e74fde0bdac1.zip qemu-34230ce5a97b898a53032b958841e74fde0bdac1.tar.gz qemu-34230ce5a97b898a53032b958841e74fde0bdac1.tar.bz2 |
i386/cpu: Don't enumerate the "invalid" CPU topology level
In the follow-up change, the CPU topology enumeration will be moved to
QAPI. And considerring "invalid" should not be exposed to QAPI as an
unsettable item, so, as a preparation for future changes, remove
"invalid" level from the current CPU topology enumeration structure
and define it by a macro instead.
Due to the removal of the enumeration of "invalid", bit 0 of
CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
level, but will start at the SMT level. Therefore, to honor this change,
update the encoding rule for CPUID[0x1F].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-2-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'include/hw/boards.h')
0 files changed, 0 insertions, 0 deletions