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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-07 14:04:26 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-07 14:04:26 +0000 |
| commit | d06dc93340825030b6297c61199a17c0067b0377 (patch) | |
| tree | c201a09b9b43ddf1b5bb811bcf69a60081030d01 /hw/timer/stm32f2xx_timer.c | |
| parent | bb5972e439dc0ac4d21329a9d97bad6760ec702d (diff) | |
| download | qemu-d06dc93340825030b6297c61199a17c0067b0377.zip qemu-d06dc93340825030b6297c61199a17c0067b0377.tar.gz qemu-d06dc93340825030b6297c61199a17c0067b0377.tar.bz2 | |
target/arm: Flush tlb for ASID changes in EL2&0 translation regime
Since we only support a single ASID, flush the tlb when it changes.
Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between
the two TTBR* registers for the location of the ASID.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/stm32f2xx_timer.c')
0 files changed, 0 insertions, 0 deletions