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| author | Arnaud Minier <arnaud.minier@telecom-paris.fr> | 2024-03-03 15:06:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-05 13:22:56 +0000 |
| commit | 6487653efd54ea16c9fa39f0f7a648f27bc2c548 (patch) | |
| tree | 85e6589cb5b15a4bcc1e5086cf57349a9b020d40 /hw/net/virtio-net.c | |
| parent | ec7d83acbd1182d47df742745b43e6b16a3a4977 (diff) | |
| download | qemu-6487653efd54ea16c9fa39f0f7a648f27bc2c548.zip qemu-6487653efd54ea16c9fa39f0f7a648f27bc2c548.tar.gz qemu-6487653efd54ea16c9fa39f0f7a648f27bc2c548.tar.bz2 | |
hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object
This object represents the PLLs and their channels. The PLLs allow for a
more fine-grained control of the clocks frequency.
The migration handling is based on hw/misc/zynq_sclr.c.
Three phase reset will be handled in a later commit.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-4-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/net/virtio-net.c')
0 files changed, 0 insertions, 0 deletions