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authorAditya Gupta <adityag@linux.ibm.com>2025-08-27 11:02:28 +0530
committerMichael Tokarev <mjt@tls.msk.ru>2025-09-03 10:57:50 +0300
commit25fef09ce17ac1ae22638a0b57d97c2bd5cd7d83 (patch)
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parent0ac122d933323610b3dc7ce846cb47ba48d78266 (diff)
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docs: fix typo in xive doc
"Interrupt Pending Buffer" IPB, which got written as IBP due to typo. The "IPB" register is also mentioned in same doc multiple times. Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'docs')
-rw-r--r--docs/specs/ppc-xive.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/specs/ppc-xive.rst b/docs/specs/ppc-xive.rst
index 83d43f6..968cc76 100644
--- a/docs/specs/ppc-xive.rst
+++ b/docs/specs/ppc-xive.rst
@@ -157,7 +157,7 @@ Interrupt flow from an O/S perspective
After an event data has been enqueued in the O/S Event Queue, the IVPE
raises the bit corresponding to the priority of the pending interrupt
-in the register IBP (Interrupt Pending Buffer) to indicate that an
+in the register IPB (Interrupt Pending Buffer) to indicate that an
event is pending in one of the 8 priority queues. The Pending
Interrupt Priority Register (PIPR) is also updated using the IPB. This
register represent the priority of the most favored pending