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| author | Troy Lee <troy_lee@aspeedtech.com> | 2025-03-17 14:59:37 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-03-23 18:42:16 +0100 |
| commit | d4dfb4ffd4008d0d7d3bc9b1dca3e5c5afcc4336 (patch) | |
| tree | 0698706bb126f873d210e3750490639e76d91bbc | |
| parent | 527dede083d3e3e5a13ee996776926e0a0c4e258 (diff) | |
| download | qemu-d4dfb4ffd4008d0d7d3bc9b1dca3e5c5afcc4336.zip qemu-d4dfb4ffd4008d0d7d3bc9b1dca3e5c5afcc4336.tar.gz qemu-d4dfb4ffd4008d0d7d3bc9b1dca3e5c5afcc4336.tar.bz2 | |
aspeed: Fix maximum number of spi controller
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
maximum number of spi controller to 2, result in ehci[0] is being
overwritten in runtime.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Fixes: 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250317065938.1902272-1-troy_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
| -rw-r--r-- | include/hw/arm/aspeed_soc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f899356..f069d17 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -42,7 +42,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" -#define ASPEED_SPIS_NUM 2 +#define ASPEED_SPIS_NUM 3 #define ASPEED_EHCIS_NUM 2 #define ASPEED_WDTS_NUM 8 #define ASPEED_CPUS_NUM 4 |