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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2025-06-04 14:43:28 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:48 +1000 |
| commit | bab2be19239bc8e586a868eafd1c78a2d55a1a58 (patch) | |
| tree | 315992f8c7e9007c7b56360867017e848ef415ee | |
| parent | f31ba686a9387640a905ac70fe682c15c461a134 (diff) | |
| download | qemu-bab2be19239bc8e586a868eafd1c78a2d55a1a58.zip qemu-bab2be19239bc8e586a868eafd1c78a2d55a1a58.tar.gz qemu-bab2be19239bc8e586a868eafd1c78a2d55a1a58.tar.bz2 | |
target/riscv/cpu.c: add 'ssstrict' to riscv, isa
'ssstrict' is a RVA23 profile-defined extension defined as follows:
"No non-conforming extensions are present. Attempts to execute
unimplemented opcodes or access unimplemented CSRs in the standard or
reserved encoding spaces raises an illegal instruction exception that
results in a contained trap to the supervisor-mode trap handler."
In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20250529202315.1684198-3-dbarboza@ventanamicro.com>
Message-ID: <20250604174329.1147549-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 1 | ||||
| -rw-r--r-- | tests/data/acpi/riscv64/virt/RHCT | bin | 406 -> 416 bytes |
2 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b4e7eff..626b0b8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -217,6 +217,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), + ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT Binary files differindex 156607d..52a4cc4 100644 --- a/tests/data/acpi/riscv64/virt/RHCT +++ b/tests/data/acpi/riscv64/virt/RHCT |