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authorPaolo Bonzini <pbonzini@redhat.com>2024-08-14 12:33:02 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2025-05-12 17:48:32 +0200
commitad441b8b7913a26b18edbc076c74ca0cdbfa4ee5 (patch)
tree648d22eca2e64af7613698b8a4acb9b830acff6b
parentc7c332831fa79c6d58ac53dab1c195041a4ba687 (diff)
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target/i386: implement TSS trap bit
Now that we can do so after the error code has been pushed, raising the #DB exception for task-switch traps is trivial. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r--target/i386/tcg/seg_helper.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index cb90ccd..071f3fb 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -473,10 +473,6 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
new_segs[R_GS] = 0;
new_trap = 0;
}
- /* XXX: avoid a compiler warning, see
- http://support.amd.com/us/Processor_TechDocs/24593.pdf
- chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
- (void)new_trap;
/* clear busy bit (it is restartable) */
if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
@@ -622,6 +618,11 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
}
SET_ESP(sa.sp, sa.sp_mask);
}
+
+ if (new_trap) {
+ env->dr[6] |= DR6_BT;
+ raise_exception_ra(env, EXCP01_DB, retaddr);
+ }
}
static void switch_tss(CPUX86State *env, int tss_selector,