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| author | Xin Li (Intel) <xin@zytor.com> | 2025-01-03 00:48:27 -0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-06-03 22:42:46 +0200 |
| commit | 91084f3b44b1da4935eec85b79c1f97d1c140ada (patch) | |
| tree | d04226c983ba92368e26ca005081c78c251dac1a | |
| parent | 99216748fd4e2b25dc0a7609e8a4fecea4c3eaf4 (diff) | |
| download | qemu-91084f3b44b1da4935eec85b79c1f97d1c140ada.zip qemu-91084f3b44b1da4935eec85b79c1f97d1c140ada.tar.gz qemu-91084f3b44b1da4935eec85b79c1f97d1c140ada.tar.bz2 | |
target/i386: Add the immediate form MSR access instruction support
The immediate form of MSR access instructions are primarily motivated by
performance, not code size: by having the MSR number in an immediate, it
is available *much* earlier in the pipeline, which allows the hardware
much more leeway about how a particular MSR is handled.
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Link: https://lore.kernel.org/r/20250103084827.1820007-4-xin@zytor.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b05f465..40aefb3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1155,7 +1155,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = CPUID_FEATURE_WORD, .feat_names = { NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "msr-imm", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0ec1cbd..545851c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1001,6 +1001,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); /* Linear Address Masking */ #define CPUID_7_1_EAX_LAM (1U << 26) +/* The immediate form of MSR access instructions */ +#define CPUID_7_1_ECX_MSR_IMM (1U << 5) + /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) /* AVX NE CONVERT Instructions */ @@ -1024,6 +1027,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_2_EDX_DDPD_U (1U << 3) /* Indicate bit 10 of the IA32_SPEC_CTRL MSR is supported */ #define CPUID_7_2_EDX_BHI_CTRL (1U << 4) + /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ #define CPUID_7_2_EDX_MCDT_NO (1U << 5) |