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| author | Max Chou <max.chou@sifive.com> | 2023-10-26 23:18:13 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
| commit | 7cdc8ddb080863c7883762961e5012f08487ce98 (patch) | |
| tree | dd79f2ab493bf87c44947a243b1127c1db7a02c9 | |
| parent | f209cb0a83cc57bb172bff4b862932a408d46b58 (diff) | |
| download | qemu-7cdc8ddb080863c7883762961e5012f08487ce98.zip qemu-7cdc8ddb080863c7883762961e5012f08487ce98.tar.gz qemu-7cdc8ddb080863c7883762961e5012f08487ce98.tar.bz2 | |
target/riscv: Add cfg properties for Zvkn[c|g] extensions
Vector crypto spec defines the NIST algorithm suite related extensions
(Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_cfg.h | 3 | ||||
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 20 |
2 files changed, 23 insertions, 0 deletions
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c4b2fec..0873300 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -98,6 +98,9 @@ struct RISCVCPUConfig { bool ext_zvksed; bool ext_zvksh; bool ext_zvkt; + bool ext_zvkn; + bool ext_zvknc; + bool ext_zvkng; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ad7a183..9540d1d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -499,6 +499,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + /* + * Shorthand vector crypto extensions + */ + if (cpu->cfg.ext_zvknc) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + + if (cpu->cfg.ext_zvkng) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); + } + + if (cpu->cfg.ext_zvkn) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); + } + if (cpu->cfg.ext_zvkt) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); |