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author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2025-07-03 11:41:09 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2025-07-10 09:11:14 +0100 |
commit | 3fd8426aefa946ac6ab86103f68c9b526a0de237 (patch) | |
tree | 4230a2bb0ad6d1c7e23fbcb94d866f9fb2f7b5bc | |
parent | 9d8ade51a20d15f3be70c821c274b081ba65cea8 (diff) | |
download | qemu-3fd8426aefa946ac6ab86103f68c9b526a0de237.zip qemu-3fd8426aefa946ac6ab86103f68c9b526a0de237.tar.gz qemu-3fd8426aefa946ac6ab86103f68c9b526a0de237.tar.bz2 |
docs/cxl: Add an arm/virt example.
Only add one very simple example as all the i386/pc examples will work
for arm/virt with a change to appropriate executable and appropriate
standard launch line for arm/virt. Note that max cpu is used to
ensure we have plenty of physical address space.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com>
Tested-by: Li Zhijian <lizhijian@fujitsu.com>
Message-id: 20250703104110.992379-5-Jonathan.Cameron@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | docs/system/devices/cxl.rst | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index e307caf..ca15a0d 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -384,6 +384,17 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,sn=0x4 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k +A simple arm/virt example featuring a single direct connected CXL Type 3 +Volatile Memory device:: + + qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8g,slots=4 -cpu max -smp 4 \ + ... + -object memory-backend-ram,id=vmem0,share=on,size=256M \ + -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ + -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ + -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0 \ + -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G + Deprecations ------------ |