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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-02-10 10:11:16 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-06 15:46:18 +0100 |
| commit | 3bbcc0f732a173f164628243c6345b659c08900d (patch) | |
| tree | 184706c819b5ea941aa252544ceba17b219ae1ca | |
| parent | 05769aae6288a69ba04b0162ed0a15b08b2b7878 (diff) | |
| download | qemu-3bbcc0f732a173f164628243c6345b659c08900d.zip qemu-3bbcc0f732a173f164628243c6345b659c08900d.tar.gz qemu-3bbcc0f732a173f164628243c6345b659c08900d.tar.bz2 | |
target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-5-philmd@linaro.org>
| -rw-r--r-- | target/riscv/cpu.c | 2 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6da3917..d4f0196 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; + mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data; riscv_cpu_validate_misa_mxl(mcc); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bd..7de19b4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -539,7 +539,7 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; - uint32_t misa_mxl_max; /* max mxl for this cpu */ + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |