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| author | Andrew Waterman <andrew@sifive.com> | 2023-03-27 15:57:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-03-27 15:58:43 -0700 |
| commit | 3ed18cfbc707c75af83941e8fdf7f68f5a3b4803 (patch) | |
| tree | 151c4a6304fd0ff3335128c30c9a4d7c02997f9b /pk | |
| parent | 573c858d9071a2216537f71de651a814f76ee76d (diff) | |
| download | pk-3ed18cfbc707c75af83941e8fdf7f68f5a3b4803.zip pk-3ed18cfbc707c75af83941e8fdf7f68f5a3b4803.tar.gz pk-3ed18cfbc707c75af83941e8fdf7f68f5a3b4803.tar.bz2 | |
Revert "Revert "SBI emulation of reads and writes to perf counters and config (#98)""
This reverts commit 7ae86fb97b792586493255f935f2f12ff068b13f.
This will continue to allow accesses to cycle/time via mcycle/mtime
despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297.
The hope is this will keep most people happy while doing the right thing
with Spike.
Diffstat (limited to 'pk')
0 files changed, 0 insertions, 0 deletions