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| author | Nicholas O'Brien <nickisobrien@gmail.com> | 2020-07-18 08:56:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-18 08:56:57 -0700 |
| commit | 6584364eaebfbad80ae91f232e7155c3c275b098 (patch) | |
| tree | 4e25c5da21517411cf5ea04af236341e2f81a0f1 | |
| parent | 5d9ed238e1cabfbca3c47f50d32894ce94bfc304 (diff) | |
| download | pk-6584364eaebfbad80ae91f232e7155c3c275b098.zip pk-6584364eaebfbad80ae91f232e7155c3c275b098.tar.gz pk-6584364eaebfbad80ae91f232e7155c3c275b098.tar.bz2 | |
Fix UART register map (#208)
While it's unused upstream, according to the SiFive FU540 document, the
UART divisor register is at offset 0x18.
This also maps the interrupt enable and interrupt pending register
offsets.
| -rw-r--r-- | machine/uart.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/machine/uart.h b/machine/uart.h index 928009d..61662fe 100644 --- a/machine/uart.h +++ b/machine/uart.h @@ -11,7 +11,9 @@ extern volatile uint32_t* uart; #define UART_REG_RXFIFO 1 #define UART_REG_TXCTRL 2 #define UART_REG_RXCTRL 3 -#define UART_REG_DIV 4 +#define UART_REG_IE 4 +#define UART_REG_IP 5 +#define UART_REG_DIV 6 #define UART_TXEN 0x1 #define UART_RXEN 0x1 |