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author | Rich Felker <dalias@aerifal.cx> | 2019-07-17 18:53:26 -0400 |
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committer | Rich Felker <dalias@aerifal.cx> | 2019-07-17 18:53:26 -0400 |
commit | 2dcbeabd917e404a0dde0195388da401b849b9a4 (patch) | |
tree | 862bee640cc32ecb954ceddfae54eda54d165c5a /arch | |
parent | 8eb49e0485fc547eead9e47200bbee6d81f391c1 (diff) | |
download | musl-2dcbeabd917e404a0dde0195388da401b849b9a4.zip musl-2dcbeabd917e404a0dde0195388da401b849b9a4.tar.gz musl-2dcbeabd917e404a0dde0195388da401b849b9a4.tar.bz2 |
fix riscv64 atomic asm constraints
most egregious problem was the lack of memory clobber and lack of
volatile asm; this made the atomics memory barriers but not compiler
barriers. use of "+r" rather than "=r" for a clobbered temp was also
wrong, since the initial value is indeterminate.
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv64/atomic_arch.h | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h index 98f12fc..d0228a3 100644 --- a/arch/riscv64/atomic_arch.h +++ b/arch/riscv64/atomic_arch.h @@ -8,13 +8,15 @@ static inline void a_barrier() static inline int a_cas(volatile int *p, int t, int s) { int old, tmp; - __asm__("\n1: lr.w.aqrl %0, %2\n" + __asm__ __volatile__ ( + "\n1: lr.w.aqrl %0, %2\n" " bne %0, %3, 1f\n" " sc.w.aqrl %1, %4, %2\n" " bnez %1, 1b\n" "1:" - : "=&r"(old), "+r"(tmp), "+A"(*p) - : "r"(t), "r"(s)); + : "=&r"(old), "=r"(tmp), "+A"(*p) + : "r"(t), "r"(s) + : "memory"); return old; } @@ -23,12 +25,14 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s) { void *old; int tmp; - __asm__("\n1: lr.d.aqrl %0, %2\n" + __asm__ __volatile__ ( + "\n1: lr.d.aqrl %0, %2\n" " bne %0, %3, 1f\n" " sc.d.aqrl %1, %4, %2\n" " bnez %1, 1b\n" "1:" - : "=&r"(old), "+r"(tmp), "+A"(*(long *)p) - : "r"(t), "r"(s)); + : "=&r"(old), "=r"(tmp), "+A"(*(long *)p) + : "r"(t), "r"(s) + : "memory"); return old; } |