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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=mem2reg,simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
define i32 @test_inline_constraint_S_label_tailmerged(i1 %in) {
; CHECK-LABEL: @test_inline_constraint_S_label_tailmerged(
; CHECK-NEXT: call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, [[COMMON_RET:%.*]]))
; CHECK-NEXT: [[COMMON_RETVAL:%.*]] = select i1 [[IN:%.*]], i32 0, i32 42
; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: common.ret:
; CHECK-NEXT: ret i32 [[COMMON_RETVAL]]
;
call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, %loc))
br i1 %in, label %loc, label %loc2
loc:
br label %common.ret
loc2:
br label %common.ret
common.ret:
%common.retval = phi i32 [ 0, %loc ], [ 42, %loc2 ]
ret i32 %common.retval
}
define i32 @test_inline_constraint_S_label_tailmerged2(i1 %in) {
; CHECK-LABEL: @test_inline_constraint_S_label_tailmerged2(
; CHECK-NEXT: common.ret:
; CHECK-NEXT: call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, [[COMMON_RET:%.*]]))
; CHECK-NEXT: [[DOT:%.*]] = select i1 [[IN:%.*]], i32 0, i32 42
; CHECK-NEXT: ret i32 [[DOT]]
;
call void asm sideeffect "adr x0, $0", "S"(ptr blockaddress(@test_inline_constraint_S_label_tailmerged, %loc))
br i1 %in, label %loc, label %loc2
common.ret:
%common.retval = phi i32 [ 0, %loc ], [ 42, %loc2 ]
ret i32 %common.retval
loc:
br label %common.ret
loc2:
br label %common.ret
}
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