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|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=indvars -S | FileCheck %s
; Indvars should be able to promote the hiPart induction variable in the
; inner loop to i64.
; TODO: it should promote hiPart to i64 in the outer loop too.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n32:64"
define void @t(ptr %pval1, ptr %peakWeight, ptr %nrgReducePeakrate, i32 %bandEdgeIndex, float %val1) nounwind {
; CHECK-LABEL: define void @t
; CHECK-SAME: (ptr [[PVAL1:%.*]], ptr [[PEAKWEIGHT:%.*]], ptr [[NRGREDUCEPEAKRATE:%.*]], i32 [[BANDEDGEINDEX:%.*]], float [[VAL1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VAL:%.*]] = load float, ptr [[PEAKWEIGHT]], align 4
; CHECK-NEXT: [[VAL2:%.*]] = icmp sgt i32 [[BANDEDGEINDEX]], 0
; CHECK-NEXT: br i1 [[VAL2]], label [[BB_NPH22:%.*]], label [[RETURN:%.*]]
; CHECK: bb.nph22:
; CHECK-NEXT: [[VAL3:%.*]] = add i32 [[BANDEDGEINDEX]], -1
; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[VAL3]] to i64
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[BANDEDGEINDEX]] to i64
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb:
; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[BB8:%.*]] ], [ 0, [[BB_NPH22]] ]
; CHECK-NEXT: [[DISTERBHI_121:%.*]] = phi float [ [[DISTERBHI_2_LCSSA:%.*]], [[BB8]] ], [ 0.000000e+00, [[BB_NPH22]] ]
; CHECK-NEXT: [[DISTERBLO_120:%.*]] = phi float [ [[DISTERBLO_0_LCSSA:%.*]], [[BB8]] ], [ 0.000000e+00, [[BB_NPH22]] ]
; CHECK-NEXT: [[HIPART_119:%.*]] = phi i32 [ [[HIPART_0_LCSSA:%.*]], [[BB8]] ], [ 0, [[BB_NPH22]] ]
; CHECK-NEXT: [[LOPART_118:%.*]] = phi i32 [ [[LOPART_0_LCSSA:%.*]], [[BB8]] ], [ 0, [[BB_NPH22]] ]
; CHECK-NEXT: [[PEAKCOUNT_117:%.*]] = phi float [ [[PEAKCOUNT_2_LCSSA:%.*]], [[BB8]] ], [ [[VAL]], [[BB_NPH22]] ]
; CHECK-NEXT: [[VAL4:%.*]] = icmp samesign ugt i64 [[INDVARS_IV1]], 0
; CHECK-NEXT: br i1 [[VAL4]], label [[BB1:%.*]], label [[BB3_PREHEADER:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
; CHECK-NEXT: [[VAL7:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[TMP1]]
; CHECK-NEXT: [[VAL8:%.*]] = load float, ptr [[VAL7]], align 4
; CHECK-NEXT: [[VAL9:%.*]] = fadd float [[VAL8]], [[DISTERBLO_120]]
; CHECK-NEXT: [[TMP2:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
; CHECK-NEXT: [[VAL12:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[TMP2]]
; CHECK-NEXT: [[VAL13:%.*]] = load float, ptr [[VAL12]], align 4
; CHECK-NEXT: [[VAL14:%.*]] = fsub float [[DISTERBHI_121]], [[VAL13]]
; CHECK-NEXT: br label [[BB3_PREHEADER]]
; CHECK: bb3.preheader:
; CHECK-NEXT: [[DISTERBLO_0_PH:%.*]] = phi float [ [[DISTERBLO_120]], [[BB]] ], [ [[VAL9]], [[BB1]] ]
; CHECK-NEXT: [[DISTERBHI_0_PH:%.*]] = phi float [ [[DISTERBHI_121]], [[BB]] ], [ [[VAL14]], [[BB1]] ]
; CHECK-NEXT: [[VAL15:%.*]] = fcmp ogt float [[DISTERBLO_0_PH]], 2.500000e+00
; CHECK-NEXT: br i1 [[VAL15]], label [[BB_NPH:%.*]], label [[BB5_PREHEADER:%.*]]
; CHECK: bb.nph:
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
; CHECK-NEXT: [[DISTERBLO_03:%.*]] = phi float [ [[VAL19:%.*]], [[BB3:%.*]] ], [ [[DISTERBLO_0_PH]], [[BB_NPH]] ]
; CHECK-NEXT: [[LOPART_02:%.*]] = phi i32 [ [[VAL24:%.*]], [[BB3]] ], [ [[LOPART_118]], [[BB_NPH]] ]
; CHECK-NEXT: [[PEAKCOUNT_01:%.*]] = phi float [ [[VAL23:%.*]], [[BB3]] ], [ [[PEAKCOUNT_117]], [[BB_NPH]] ]
; CHECK-NEXT: [[VAL16:%.*]] = sext i32 [[LOPART_02]] to i64
; CHECK-NEXT: [[VAL17:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[VAL16]]
; CHECK-NEXT: [[VAL18:%.*]] = load float, ptr [[VAL17]], align 4
; CHECK-NEXT: [[VAL19]] = fsub float [[DISTERBLO_03]], [[VAL18]]
; CHECK-NEXT: [[VAL20:%.*]] = sext i32 [[LOPART_02]] to i64
; CHECK-NEXT: [[VAL21:%.*]] = getelementptr float, ptr [[PEAKWEIGHT]], i64 [[VAL20]]
; CHECK-NEXT: [[VAL22:%.*]] = load float, ptr [[VAL21]], align 4
; CHECK-NEXT: [[VAL23]] = fsub float [[PEAKCOUNT_01]], [[VAL22]]
; CHECK-NEXT: [[VAL24]] = add i32 [[LOPART_02]], 1
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[VAL25:%.*]] = fcmp ogt float [[VAL19]], 2.500000e+00
; CHECK-NEXT: br i1 [[VAL25]], label [[BB2]], label [[BB3_BB5_PREHEADER_CRIT_EDGE:%.*]]
; CHECK: bb3.bb5.preheader_crit_edge:
; CHECK-NEXT: [[VAL24_LCSSA:%.*]] = phi i32 [ [[VAL24]], [[BB3]] ]
; CHECK-NEXT: [[VAL23_LCSSA:%.*]] = phi float [ [[VAL23]], [[BB3]] ]
; CHECK-NEXT: [[VAL19_LCSSA:%.*]] = phi float [ [[VAL19]], [[BB3]] ]
; CHECK-NEXT: br label [[BB5_PREHEADER]]
; CHECK: bb5.preheader:
; CHECK-NEXT: [[DISTERBLO_0_LCSSA]] = phi float [ [[VAL19_LCSSA]], [[BB3_BB5_PREHEADER_CRIT_EDGE]] ], [ [[DISTERBLO_0_PH]], [[BB3_PREHEADER]] ]
; CHECK-NEXT: [[LOPART_0_LCSSA]] = phi i32 [ [[VAL24_LCSSA]], [[BB3_BB5_PREHEADER_CRIT_EDGE]] ], [ [[LOPART_118]], [[BB3_PREHEADER]] ]
; CHECK-NEXT: [[PEAKCOUNT_0_LCSSA:%.*]] = phi float [ [[VAL23_LCSSA]], [[BB3_BB5_PREHEADER_CRIT_EDGE]] ], [ [[PEAKCOUNT_117]], [[BB3_PREHEADER]] ]
; CHECK-NEXT: [[DOTNOT10:%.*]] = fcmp olt float [[DISTERBHI_0_PH]], 2.500000e+00
; CHECK-NEXT: [[VAL26:%.*]] = icmp sgt i32 [[VAL3]], [[HIPART_119]]
; CHECK-NEXT: [[OR_COND11:%.*]] = and i1 [[VAL26]], [[DOTNOT10]]
; CHECK-NEXT: br i1 [[OR_COND11]], label [[BB_NPH12:%.*]], label [[BB7:%.*]]
; CHECK: bb.nph12:
; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[HIPART_119]] to i64
; CHECK-NEXT: br label [[BB4:%.*]]
; CHECK: bb4:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BB5:%.*]] ], [ [[TMP3]], [[BB_NPH12]] ]
; CHECK-NEXT: [[DISTERBHI_29:%.*]] = phi float [ [[VAL30:%.*]], [[BB5]] ], [ [[DISTERBHI_0_PH]], [[BB_NPH12]] ]
; CHECK-NEXT: [[PEAKCOUNT_27:%.*]] = phi float [ [[VAL35:%.*]], [[BB5]] ], [ [[PEAKCOUNT_0_LCSSA]], [[BB_NPH12]] ]
; CHECK-NEXT: [[VAL28:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[INDVARS_IV]]
; CHECK-NEXT: [[VAL29:%.*]] = load float, ptr [[VAL28]], align 4
; CHECK-NEXT: [[VAL30]] = fadd float [[VAL29]], [[DISTERBHI_29]]
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[VAL33:%.*]] = getelementptr float, ptr [[PEAKWEIGHT]], i64 [[INDVARS_IV_NEXT]]
; CHECK-NEXT: [[VAL34:%.*]] = load float, ptr [[VAL33]], align 4
; CHECK-NEXT: [[VAL35]] = fadd float [[VAL34]], [[PEAKCOUNT_27]]
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOTNOT:%.*]] = fcmp olt float [[VAL30]], 2.500000e+00
; CHECK-NEXT: [[VAL36:%.*]] = icmp sgt i64 [[TMP0]], [[INDVARS_IV_NEXT]]
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[VAL36]], [[DOTNOT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[BB4]], label [[BB5_BB7_CRIT_EDGE:%.*]]
; CHECK: bb5.bb7_crit_edge:
; CHECK-NEXT: [[VAL35_LCSSA:%.*]] = phi float [ [[VAL35]], [[BB5]] ]
; CHECK-NEXT: [[VAL31_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[BB5]] ]
; CHECK-NEXT: [[VAL30_LCSSA:%.*]] = phi float [ [[VAL30]], [[BB5]] ]
; CHECK-NEXT: [[TMP4:%.*]] = trunc nsw i64 [[VAL31_LCSSA_WIDE]] to i32
; CHECK-NEXT: br label [[BB7]]
; CHECK: bb7:
; CHECK-NEXT: [[DISTERBHI_2_LCSSA]] = phi float [ [[VAL30_LCSSA]], [[BB5_BB7_CRIT_EDGE]] ], [ [[DISTERBHI_0_PH]], [[BB5_PREHEADER]] ]
; CHECK-NEXT: [[HIPART_0_LCSSA]] = phi i32 [ [[TMP4]], [[BB5_BB7_CRIT_EDGE]] ], [ [[HIPART_119]], [[BB5_PREHEADER]] ]
; CHECK-NEXT: [[PEAKCOUNT_2_LCSSA]] = phi float [ [[VAL35_LCSSA]], [[BB5_BB7_CRIT_EDGE]] ], [ [[PEAKCOUNT_0_LCSSA]], [[BB5_PREHEADER]] ]
; CHECK-NEXT: [[VAL37:%.*]] = fadd float [[DISTERBLO_0_LCSSA]], [[DISTERBHI_2_LCSSA]]
; CHECK-NEXT: [[VAL38:%.*]] = fdiv float [[PEAKCOUNT_2_LCSSA]], [[VAL37]]
; CHECK-NEXT: [[VAL39:%.*]] = fmul float [[VAL38]], [[VAL1]]
; CHECK-NEXT: [[VAL40:%.*]] = fmul float [[VAL39]], [[VAL39]]
; CHECK-NEXT: [[VAL41:%.*]] = fmul float [[VAL40]], [[VAL40]]
; CHECK-NEXT: [[VAL42:%.*]] = fadd float [[VAL41]], 1.000000e+00
; CHECK-NEXT: [[VAL43:%.*]] = fdiv float 1.000000e+00, [[VAL42]]
; CHECK-NEXT: [[VAL45:%.*]] = getelementptr float, ptr [[NRGREDUCEPEAKRATE]], i64 [[INDVARS_IV1]]
; CHECK-NEXT: store float [[VAL43]], ptr [[VAL45]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
; CHECK-NEXT: br label [[BB8]]
; CHECK: bb8:
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT2]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB]], label [[BB8_RETURN_CRIT_EDGE:%.*]]
; CHECK: bb8.return_crit_edge:
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
; CHECK-NEXT: ret void
;
entry:
%val = load float, ptr %peakWeight, align 4 ; <float> [#uses=1]
%val2 = icmp sgt i32 %bandEdgeIndex, 0 ; <i1> [#uses=1]
br i1 %val2, label %bb.nph22, label %return
bb.nph22: ; preds = %entry
%val3 = add i32 %bandEdgeIndex, -1 ; <i32> [#uses=2]
br label %bb
bb: ; preds = %bb8, %bb.nph22
%distERBhi.121 = phi float [ %distERBhi.2.lcssa, %bb8 ], [ 0.000000e+00, %bb.nph22 ] ; <float> [#uses=2]
%distERBlo.120 = phi float [ %distERBlo.0.lcssa, %bb8 ], [ 0.000000e+00, %bb.nph22 ] ; <float> [#uses=2]
%hiPart.119 = phi i32 [ %hiPart.0.lcssa, %bb8 ], [ 0, %bb.nph22 ] ; <i32> [#uses=3]
%loPart.118 = phi i32 [ %loPart.0.lcssa, %bb8 ], [ 0, %bb.nph22 ] ; <i32> [#uses=2]
%peakCount.117 = phi float [ %peakCount.2.lcssa, %bb8 ], [ %val, %bb.nph22 ] ; <float> [#uses=2]
%part.016 = phi i32 [ %val46, %bb8 ], [ 0, %bb.nph22 ] ; <i32> [#uses=5]
%val4 = icmp sgt i32 %part.016, 0 ; <i1> [#uses=1]
br i1 %val4, label %bb1, label %bb3.preheader
bb1: ; preds = %bb
%val5 = add i32 %part.016, -1 ; <i32> [#uses=1]
%val6 = sext i32 %val5 to i64 ; <i64> [#uses=1]
%val7 = getelementptr float, ptr %pval1, i64 %val6 ; <ptr> [#uses=1]
%val8 = load float, ptr %val7, align 4 ; <float> [#uses=1]
%val9 = fadd float %val8, %distERBlo.120 ; <float> [#uses=1]
%val10 = add i32 %part.016, -1 ; <i32> [#uses=1]
%val11 = sext i32 %val10 to i64 ; <i64> [#uses=1]
%val12 = getelementptr float, ptr %pval1, i64 %val11 ; <ptr> [#uses=1]
%val13 = load float, ptr %val12, align 4 ; <float> [#uses=1]
%val14 = fsub float %distERBhi.121, %val13 ; <float> [#uses=1]
br label %bb3.preheader
bb3.preheader: ; preds = %bb1, %bb
%distERBlo.0.ph = phi float [ %distERBlo.120, %bb ], [ %val9, %bb1 ] ; <float> [#uses=3]
%distERBhi.0.ph = phi float [ %distERBhi.121, %bb ], [ %val14, %bb1 ] ; <float> [#uses=3]
%val15 = fcmp ogt float %distERBlo.0.ph, 2.500000e+00 ; <i1> [#uses=1]
br i1 %val15, label %bb.nph, label %bb5.preheader
bb.nph: ; preds = %bb3.preheader
br label %bb2
bb2: ; preds = %bb3, %bb.nph
%distERBlo.03 = phi float [ %val19, %bb3 ], [ %distERBlo.0.ph, %bb.nph ] ; <float> [#uses=1]
%loPart.02 = phi i32 [ %val24, %bb3 ], [ %loPart.118, %bb.nph ] ; <i32> [#uses=3]
%peakCount.01 = phi float [ %val23, %bb3 ], [ %peakCount.117, %bb.nph ] ; <float> [#uses=1]
%val16 = sext i32 %loPart.02 to i64 ; <i64> [#uses=1]
%val17 = getelementptr float, ptr %pval1, i64 %val16 ; <ptr> [#uses=1]
%val18 = load float, ptr %val17, align 4 ; <float> [#uses=1]
%val19 = fsub float %distERBlo.03, %val18 ; <float> [#uses=3]
%val20 = sext i32 %loPart.02 to i64 ; <i64> [#uses=1]
%val21 = getelementptr float, ptr %peakWeight, i64 %val20 ; <ptr> [#uses=1]
%val22 = load float, ptr %val21, align 4 ; <float> [#uses=1]
%val23 = fsub float %peakCount.01, %val22 ; <float> [#uses=2]
%val24 = add i32 %loPart.02, 1 ; <i32> [#uses=2]
br label %bb3
bb3: ; preds = %bb2
%val25 = fcmp ogt float %val19, 2.500000e+00 ; <i1> [#uses=1]
br i1 %val25, label %bb2, label %bb3.bb5.preheader_crit_edge
bb3.bb5.preheader_crit_edge: ; preds = %bb3
%val24.lcssa = phi i32 [ %val24, %bb3 ] ; <i32> [#uses=1]
%val23.lcssa = phi float [ %val23, %bb3 ] ; <float> [#uses=1]
%val19.lcssa = phi float [ %val19, %bb3 ] ; <float> [#uses=1]
br label %bb5.preheader
bb5.preheader: ; preds = %bb3.bb5.preheader_crit_edge, %bb3.preheader
%distERBlo.0.lcssa = phi float [ %val19.lcssa, %bb3.bb5.preheader_crit_edge ], [ %distERBlo.0.ph, %bb3.preheader ] ; <float> [#uses=2]
%loPart.0.lcssa = phi i32 [ %val24.lcssa, %bb3.bb5.preheader_crit_edge ], [ %loPart.118, %bb3.preheader ] ; <i32> [#uses=1]
%peakCount.0.lcssa = phi float [ %val23.lcssa, %bb3.bb5.preheader_crit_edge ], [ %peakCount.117, %bb3.preheader ] ; <float> [#uses=2]
%.not10 = fcmp olt float %distERBhi.0.ph, 2.500000e+00 ; <i1> [#uses=1]
%val26 = icmp sgt i32 %val3, %hiPart.119 ; <i1> [#uses=1]
%or.cond11 = and i1 %val26, %.not10 ; <i1> [#uses=1]
br i1 %or.cond11, label %bb.nph12, label %bb7
bb.nph12: ; preds = %bb5.preheader
br label %bb4
bb4: ; preds = %bb5, %bb.nph12
%distERBhi.29 = phi float [ %val30, %bb5 ], [ %distERBhi.0.ph, %bb.nph12 ] ; <float> [#uses=1]
%hiPart.08 = phi i32 [ %val31, %bb5 ], [ %hiPart.119, %bb.nph12 ] ; <i32> [#uses=2]
%peakCount.27 = phi float [ %val35, %bb5 ], [ %peakCount.0.lcssa, %bb.nph12 ] ; <float> [#uses=1]
%val27 = sext i32 %hiPart.08 to i64 ; <i64> [#uses=1]
%val28 = getelementptr float, ptr %pval1, i64 %val27 ; <ptr> [#uses=1]
%val29 = load float, ptr %val28, align 4 ; <float> [#uses=1]
%val30 = fadd float %val29, %distERBhi.29 ; <float> [#uses=3]
%val31 = add i32 %hiPart.08, 1 ; <i32> [#uses=4]
%val32 = sext i32 %val31 to i64 ; <i64> [#uses=1]
%val33 = getelementptr float, ptr %peakWeight, i64 %val32 ; <ptr> [#uses=1]
%val34 = load float, ptr %val33, align 4 ; <float> [#uses=1]
%val35 = fadd float %val34, %peakCount.27 ; <float> [#uses=2]
br label %bb5
bb5: ; preds = %bb4
%.not = fcmp olt float %val30, 2.500000e+00 ; <i1> [#uses=1]
%val36 = icmp sgt i32 %val3, %val31 ; <i1> [#uses=1]
%or.cond = and i1 %val36, %.not ; <i1> [#uses=1]
br i1 %or.cond, label %bb4, label %bb5.bb7_crit_edge
bb5.bb7_crit_edge: ; preds = %bb5
%val35.lcssa = phi float [ %val35, %bb5 ] ; <float> [#uses=1]
%val31.lcssa = phi i32 [ %val31, %bb5 ] ; <i32> [#uses=1]
%val30.lcssa = phi float [ %val30, %bb5 ] ; <float> [#uses=1]
br label %bb7
bb7: ; preds = %bb5.bb7_crit_edge, %bb5.preheader
%distERBhi.2.lcssa = phi float [ %val30.lcssa, %bb5.bb7_crit_edge ], [ %distERBhi.0.ph, %bb5.preheader ] ; <float> [#uses=2]
%hiPart.0.lcssa = phi i32 [ %val31.lcssa, %bb5.bb7_crit_edge ], [ %hiPart.119, %bb5.preheader ] ; <i32> [#uses=1]
%peakCount.2.lcssa = phi float [ %val35.lcssa, %bb5.bb7_crit_edge ], [ %peakCount.0.lcssa, %bb5.preheader ] ; <float> [#uses=2]
%val37 = fadd float %distERBlo.0.lcssa, %distERBhi.2.lcssa ; <float> [#uses=1]
%val38 = fdiv float %peakCount.2.lcssa, %val37 ; <float> [#uses=1]
%val39 = fmul float %val38, %val1 ; <float> [#uses=2]
%val40 = fmul float %val39, %val39 ; <float> [#uses=2]
%val41 = fmul float %val40, %val40 ; <float> [#uses=1]
%val42 = fadd float %val41, 1.000000e+00 ; <float> [#uses=1]
%val43 = fdiv float 1.000000e+00, %val42 ; <float> [#uses=1]
%val44 = sext i32 %part.016 to i64 ; <i64> [#uses=1]
%val45 = getelementptr float, ptr %nrgReducePeakrate, i64 %val44 ; <ptr> [#uses=1]
store float %val43, ptr %val45, align 4
%val46 = add i32 %part.016, 1 ; <i32> [#uses=2]
br label %bb8
bb8: ; preds = %bb7
%val47 = icmp slt i32 %val46, %bandEdgeIndex ; <i1> [#uses=1]
br i1 %val47, label %bb, label %bb8.return_crit_edge
bb8.return_crit_edge: ; preds = %bb8
br label %return
return: ; preds = %bb8.return_crit_edge, %entry
ret void
}
|
