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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s
define void @PR91005(ptr %0) minsize {
; CHECK-LABEL: PR91005:
; CHECK: # %bb.0:
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: movl $31744, %eax # imm = 0x7C00
; CHECK-NEXT: vmovd %eax, %xmm0
; CHECK-NEXT: vpcmpeqw %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpinsrw $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; CHECK-NEXT: vpextrw $0, %xmm0, (%rdi)
; CHECK-NEXT: .LBB0_2: # %common.ret
; CHECK-NEXT: retq
%2 = bitcast <2 x half> poison to <2 x i16>
%3 = icmp eq <2 x i16> %2, <i16 31744, i16 31744>
br i1 poison, label %4, label %common.ret
common.ret: ; preds = %4, %1
ret void
4: ; preds = %1
%5 = select <2 x i1> %3, <2 x half> <half 0xH3C00, half 0xH3C00>, <2 x half> zeroinitializer
%6 = fmul <2 x half> %5, zeroinitializer
%7 = fsub <2 x half> %6, zeroinitializer
%8 = extractelement <2 x half> %7, i64 0
store half %8, ptr %0, align 2
br label %common.ret
}
declare <2 x half> @llvm.fabs.v2f16(<2 x half>)
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