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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
;
; Reproducer from https://github.com/llvm/llvm-project/issues/76416
;
@load_p = external global ptr, align 8
@load_data = external global i8, align 1
define dso_local void @pr76416() {
; CHECK-LABEL: pr76416:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: jg .LBB0_3
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: jle .LBB0_2
; CHECK-NEXT: .LBB0_3: # %for.end
; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq load_p@GOTPCREL(%rip), %rax
; CHECK-NEXT: movq load_data@GOTPCREL(%rip), %rcx
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_4: # %for.cond1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movq (%rax), %rdx
; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: movzbl (%rdx,%rsi), %edx
; CHECK-NEXT: movb %dl, (%rcx)
; CHECK-NEXT: leal 1(%rsi), %edx
; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: jmp .LBB0_4
entry:
%alloca = alloca i32, align 4
store i32 0, ptr %alloca, align 4
br label %for.cond
for.cond: ; preds = %for.body, %entry
%load.from.alloca.0 = load i32, ptr %alloca, align 4
%cmp = icmp slt i32 %load.from.alloca.0, 4
br i1 %cmp, label %for.body, label %for.end
for.body: ; preds = %for.cond
call void asm sideeffect "", "{ax},~{dirflag},~{fpsr},~{flags}"(i8 0) nounwind
%load.from.alloca.1 = load i32, ptr %alloca, align 4
%inc = add nsw i32 %load.from.alloca.1, 1
store i32 %inc, ptr %alloca, align 4
br label %for.cond
for.end: ; preds = %for.cond
store i32 0, ptr %alloca, align 4
br label %for.cond1
for.cond1: ; preds = %for.cond1, %for.end
call void asm sideeffect "", "N{dx},~{dirflag},~{fpsr},~{flags}"(i32 poison) nounwind
%load.from.load_p = load ptr, ptr @load_p, align 8
%regs = getelementptr inbounds { [4 x i8] }, ptr %load.from.load_p, i32 0, i32 0
%load.from.alloca.2 = load i32, ptr %alloca, align 4
%idxprom = sext i32 %load.from.alloca.2 to i64
%arrayidx = getelementptr inbounds [4 x i8], ptr %regs, i64 0, i64 %idxprom
%load.with.gep.ptr = load i8, ptr %arrayidx, align 1
store i8 %load.with.gep.ptr, ptr @load_data, align 1
%load.from.alloca.3 = load i32, ptr %alloca, align 4
%inc2 = add nsw i32 %load.from.alloca.3, 1
store i32 %inc2, ptr %alloca, align 4
br label %for.cond1
}
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