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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=x86_64-- -mattr=+avx2 -run-pass=peephole-opt -o - %s | FileCheck %s
# When trying to coalesce the operand of VMOVSDto64rr, a query would
# be made with the same register class but the source has a
# subregister and the result does not.
---
name: uncoalescable_copy_queries_same_regclass_with_only_one_subreg
tracksRegLiveness: true
isSSA: true
body: |
bb.0:
liveins: $rax
; CHECK-LABEL: name: uncoalescable_copy_queries_same_regclass_with_only_one_subreg
; CHECK: liveins: $rax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rax
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[COPY]].sub_32bit
; CHECK-NEXT: [[VMOVSDto64rr:%[0-9]+]]:gr64 = VMOVSDto64rr [[COPY1]]
; CHECK-NEXT: RET 0, implicit [[VMOVSDto64rr]]
%0:gr64 = COPY $rax
%1:vr128 = COPY %0.sub_32bit
%2:gr64 = VMOVSDto64rr %1
RET 0, implicit %2
...
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