aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/X86/pr40090.ll
blob: af933c950e11175692c2903b03de6decfce21ab4 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s

define i64 @foo(i64 %x, i64 %y) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0:
; CHECK-NEXT:    bsrq %rdi, %rcx
; CHECK-NEXT:    orq $64, %rcx
; CHECK-NEXT:    bsrq %rsi, %rcx
; CHECK-NEXT:    movl $63, %eax
; CHECK-NEXT:    subq %rcx, %rax
; CHECK-NEXT:    retq
  %1 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
  %2 = xor i64 %1, 127
  %3 = tail call i64 @llvm.ctlz.i64(i64 %y, i1 true)
  %4 = xor i64 %3, 63
  %5 = icmp eq i64 %y, 0
  %6 = select i1 %5, i64 %2, i64 %4
  %7 = sub nsw i64 63, %6
  ret i64 %7
}

define i64 @bar(i64 %x, i64 %y) {
; CHECK-LABEL: bar:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl $127, %ecx
; CHECK-NEXT:    bsrq %rdi, %rcx
; CHECK-NEXT:    xorq $64, %rcx
; CHECK-NEXT:    bsrq %rsi, %rcx
; CHECK-NEXT:    movl $63, %eax
; CHECK-NEXT:    subq %rcx, %rax
; CHECK-NEXT:    retq
  %1 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
  %2 = xor i64 %1, 127
  %3 = tail call i64 @llvm.ctlz.i64(i64 %y, i1 false)
  %4 = xor i64 %3, 63
  %5 = icmp eq i64 %y, 0
  %6 = select i1 %5, i64 %2, i64 %4
  %7 = sub nsw i64 63, %6
  ret i64 %7
}

declare i64 @llvm.ctlz.i64(i64, i1)