blob: f2d3bc8217b1d103a0a7e1a14150aad3314c43b3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefixes=CHECK,X64
; It doesn't matter if an x86-64 target has specified "no-sse2"; we still can use mfence.
define void @test() {
; X86-LABEL: test:
; X86: # %bb.0:
; X86-NEXT: mfence
; X86-NEXT: retl
;
; X64-LABEL: test:
; X64: # %bb.0:
; X64-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
; X64-NEXT: retq
fence seq_cst
ret void
}
define i32 @fence(ptr %ptr) {
; X86-LABEL: fence:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mfence
; X86-NEXT: movl (%eax), %eax
; X86-NEXT: retl
;
; X64-LABEL: fence:
; X64: # %bb.0:
; X64-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
; X64-NEXT: movl (%rdi), %eax
; X64-NEXT: retq
%atomic = atomicrmw add ptr %ptr, i32 0 seq_cst
ret i32 %atomic
}
define void @mfence() nounwind {
; CHECK-LABEL: mfence:
; CHECK: # %bb.0:
; CHECK-NEXT: mfence
; CHECK-NEXT: ret{{[l|q]}}
call void @llvm.x86.sse2.mfence()
ret void
}
declare void @llvm.x86.sse2.mfence() nounwind readnone
|
